| RQL: global placement via relaxed quadratic spreading and linearization |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 44th annual Design Automation Conference
table of contents
San Diego, California
SESSION: Modern placement techniques
table of contents
Pages: 453 - 458
Year of Publication: 2007
ISBN ~ ISSN:0738-100X , 978-1-59593-627-1
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Authors
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Natarajan Viswanathan
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IBM Corporation, Austin, TX and Iowa State University, Ames, IA
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Gi-Joon Nam
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IBM Corporation, Austin, TX
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Charles J. Alpert
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IBM Corporation, Austin, TX
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Paul Villarrubia
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IBM Corporation, Austin, TX
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Haoxing Ren
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IBM Corporation, Austin, TX
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Chris Chu
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Iowa State University, Ames, IA
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Downloads (6 Weeks): 5, Downloads (12 Months): 26, Citation Count: 2
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ABSTRACT
This paper describes a simple and effective quadratic placement algorithm called RQL. We show that a good quadratic placement, followed by local wirelength-driven spreading can produce excellent results on large-scale industrial ASIC designs. As opposed to the current top performing academic placers [4, 7, 11], RQL does not embed a linearization technique within the solver. Instead, it only requires a simpler, pure quadratic objective function in the spirit of [8, 10, 23]. Experimental results show that RQL outperforms all available academic placers on the ISPD-2005 placement contest benchmarks. In particular, RQL obtains an average wire-length improvement of 2.8%, 3.2%, 5.4%, 8.5%, and 14.6% versus mPL6 [5], NTUPlace3 [7], Kraftwerk [20], APlace2.0 [11], and Capo10.2 [18], respectively. In addition, RQL is three, seven, and ten times faster than mpL6, Capo10.2, and APlace2.0, respectively. On the ISPD-2006 placement contest benchmarks, on average, RQL obtains the best scaled wirelength among all available academic placers.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 2
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Taneem Ahmed , Paul D. Kundarewich , Jason H. Anderson , Brad L. Taylor , Rajat Aggarwal, Architecture-specific packing for virtex-5 FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
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