Characterizing process variation in nanometer CMOS

ABSTRACT

The correlation of a statistical analysis tool to hardware depends on the accuracy of underlying variation models. The models should represent actual process behavior as measured in silicon. In this paper, we present an overview of test structures for characterizing statistical variation of process parameters. We discuss the test structure design and characterization strategy for calibrating random and layout dependent systematic components of process variation. We also show measurement results from several fabricated structures in 65-nm CMOS technologies.

REFERENCES

• 1: L. W. Liebmann et al., "TCAD Development for Lithography Resolution Enhancement", IBM J. of Res. and Dev., vol. 45, pp. 651--665, Sep 2001.
• 2: L. W. Liebmann, "Resolution Enhancement Techniques in Optical Lithography, It's not Just a Mask Problem", SPIE, vol. 4409, pp. 23--32, 2001.
• 3: R. W. Keyes, "The Impact of Randomness in the Distribution of Impurity Atoms on FET Threshold", J. of App. Phys, 1975, pp. 251--259.
• 4: T. B. Hook et al., 'Lateral Ion Implant Straggle and Mask Proximity Effect", IEEE Trans on Elec. Devices, vol. 50, pp. 1946--1951, Sep 2003.
• 5: Victor Moroz , Lee Smith , Xi-Wei Lin , Dipu Pramanik , Greg Rollins, Stress-Aware Design Methodology, Proceedings of the 7th International Symposium on Quality Electronic Design, p.807-812, March 27-29, 2006 [doi>10.1109/ISQED.2006.124]
• 6: P. J. Timans et al., "Challenges for Ultra-Shallow Junction Formation Technologies beyond the 90nm Node", Intl. Conf. on Adv. Thermal Processing of Semiconductors, pp. 17--33, Sep 2003.
• 7: I. Ahsan et al., "RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology," Symp. on VLSI Technology, pp. 170--171, 2006.
• 8: K. Agarwal et al., "A Test Structure for Characterizing Local Device Mismatches", Symp. on VLSI Circuits, pp. 67--68, 2006.
• 9: K. Agarwal, S. Nassif, F. Liu, J. Hayes and K. Nowka, "Rapid Characterization of Threshold Voltage Fluctuation in MOS Devices", Intl. Conf. on Microelectronic Test Structures, 2007.
• 10: P. Oldiges et al., "Modeling Line Edge Roughness Effects in sub 100 Nanometer Gate Length Devices", SISPAD, pp. 131--134, 2000.
• 11: D. Burnett, K. Erington, C. Subramanian, K. Baker, "Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits", Symp. on VLSI Technology, pp. 15--16, 1994.
• 12: Y. Borodovsky, "Impact of Local Partial Coherence Variations on Exposure Tool Performance", SPIE, vol. 2440, pp. 750--770, 1995.
• 13: Timothy A. Brunner, Impact of lens aberrations on optical lithography, IBM Journal of Research and Development, v.41 n.1-2, p.57-67, Jan./March 1997
• 14: A. K. Wong, R. Ferguson and S. Mansfield, "Mask Error Factor in Optical Lithography", IEEE Trans. on Semiconductor Manuf., vol. 13, pp. 235--242, May 2000.
• 15: C. Hedlund, H. Blom and S. Berg, "Microloading Effect in Reactive Ion Etching," J. of Vacuum Science and Tech., vol. 12, pp. 1962--1965, 1994.
• 16: J. Watts, N. Lu, C. Bittner, S. Grundon and J. Oppold, "Modeling FET Variation within a Chip as a Function of Circuit Design and Layout Choices", Nanotech Workshop on Compact Modeling, pp. 87--92, 2005.
• 17: L. Liebmann et al., "High Performance Circuit Design for the RET-Enabled 65-nm Technology Node", SPIE, vol. 5379, 2004.
• 18: M. Lavin , Fook-Luen Heng , G. Northrop, Backend CAD flows for "restrictive design rules", Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.739-746, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382674]
• 19: J. Watts, K.-W. Su and M. Basel, "Netlisting and Modeling Well-Proximity Effects", IEEE Trans on Elec. Dev., vol. 53, pp. 2179--2186, Sep 2006.
• 20: H. S. Yang et al., "Dual Stress Liner for High Performance Sub-45nm Gate Length SOI CMOS Manufacturing", IEDM, pp. 1075--1077, 2004.
• 21: T. Ghani et al., "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors", IEDM, pp. 11.6.1--11.6.3, 2003.
• 22: C.-H. Chen et al., "Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High- Performance Strained-Si Device Application", Symp. on VLSI Technology, pp. 56--57, 2007.
• 23: G. Scott, J. Lutze, M. Rubin, F. Nouri and M. Manley, "NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress," IEDM, pp. 827--830, 1999.
• 24: M. Bhushan, A. Gattiker, M. B. Ketchen and K. K. Das, 'Ring Oscillators for CMOS Process Tuning and Variability Control", IEEE Trans. on Semiconductor Manuf., vol. 19, pp. 10--18, Feb. 2006.
• 25: M. B. Ketchen , M. Bhushan, Product-representative "At speed" test structures for CMOS characterization, IBM Journal of Research and Development, v.50 n.4/5, p.451-468, July 2006
• 26: J.-Y. Lai, N. Saka and J.-H. Chun, "Evolution of Copper-Oxide Damascene Structures in Chemical Mechanical Polishing", J. of Electrochem. Soc., pp. G31--G40, 2002.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Measurement, Performance, Reliability

Keywords:
characterization, modeling, test structure, variation