A self-tuning configurable cache

ABSTRACT

The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can reduce memory subsystem energy by 62% on average. We introduce a self-tuning cache that performs transparent runtime cache tuning, thus relieving the application designer and/or compiler from predetermining an application's cache configuration. The self-tuning cache applies tuning at a determined tuning interval. A good interval balances tuning process energy overhead against the energy overhead of running in a sub-optimal cache configuration, which we show wastes much energy. We present a self-tuning cache that dynamically varies the tuning interval, resulting in average energy reduction of as much as 29%, falling within 13% of an oracle-based optimal method.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES

General Terms:
Algorithms, Design

Keywords:
architecture tuning, cache tuning, configurable cache, embedded systems, low energy, low power, phase-based, reconfigurable architecture, reconfigurable cache