Statistical analysis of full-chip leakage power considering junction tunneling leakage

ABSTRACT

In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent total leakage power of a large circuit block, considering Ijunc, sub-threshold leakage (Isub), and gate oxide leakage (Igate). We then propose our algorithm to estimate the full-chip leakage power with consideration of both Gaussian and non-Gaussian parameter distributions, capturing spatial correlations using a grid-based model. Experiments on ISCAS85 benchmarks demonstrate that the estimated results are very accurate and efficient. For a circuit with G gates, the complexity of our approach is O(G).

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance, Reliability

Keywords:
gaussian and non-Gaussian parameter distributions, junction tunneling leakage, statistical analysis