Width-dependent statistical leakage modeling for random dopant induced threshold voltage shift

ABSTRACT

Statistical behavior of device leakage and threshold voltage shows a strong width dependency under microscopic random dopant fluctuation. Leakage estimation using the conventional square-root method shows a discrepancy as large as 45% compared to the real case because it fails to model the effective VT shift in the subthreshold region. This paper presents a width-dependent statistical leakage model with an estimation error less than 5%. Design examples on SRAMs and domino circuits demonstrate the significance of the proposed model.

REFERENCES

• 1: S. Borkar, "Circuit techniques for subthreshold leakage avoidance, control and tolerance," IEEE International Electron Devices Meeting, pp. 421--424, 2004.
• 2: Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775920]
• 3: H. Mahmoodi, S. Mukhopadhyay, K. Roy, "Estimation of Delay Variations due to Random-Dopant Fluctuations in Nanoscale CMOS Circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1787--1796, 2005.
• 4: A. Asenov, S. Kaya, J. H. Daview, "Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations," IEEE Transactions on electron devices, vol. 49, no. 1, pp. 112--119, 2002.
• 5: Yuan Taur , Tak H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, New York, NY, 1998
• 6: A. Alvandpour, D. Somasekhar, R. Krishnamurthy, V. De, S. Borkar, C. Svensson, "Bitline leakage equalization for sub-100nm caches," European Solid-State Circuits Conference, pp. 401--404, 2003.
• 7: C. H. Kim, K. Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, S. Borkar, "A process variation compensating technique for sub-90nm dynamic circuits," Symposium on VLSI Circuits, pp. 205--206, 2003.
• 8: Hongliang Chang , Sachin S. Sapatnekar, Full-chip analysis of leakage power under process variations, including spatial correlations, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065716]
• 9: E. Acar, K. Agarwal and S. R. Nassif, "Characterization of total chip leakage using inverse (reciprocal) gamma distribution," IEEE International Symposium on Circuits and Systems, pp. 3029--3032, 2006.
• 10: J. Gu, J. Keane, S. Sapatnekar and C. Kim, "Width quantization aware FinFET circuit design," Custom Integrated Circuit Conference, pp. 337--341, 2006.
• 11: A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "Atomistic" simulation study," IEEE Transactions on Electron Devices, vol. 45, no. 12, pp. 2505--2513, 1998.
• 12: H. Wong and Y. Taur, "Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 μm MOSFET's:, International Electron Devices Meeting, pp. 705--708, 1993.
• 13: Dieter K. Schroder, Semiconductor Material and Device Characterization, Wiley-Interscience, 2006
• 14: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433--1440, 1989.
• 15: K. Takeuchi, T. Tatsumi and A. Furukawa, "Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation," International Electron Device Meeting, pp. 841--844, 1997.
• 16: Predictive Technology Model, online: http://www.eas.asu.edu/~ptm/.
• 17: H. Stark and J. W. Woods, Probability and random process with applications to signal processing, Prentice Hall, 2002
• 18: H. Mahmoodi-Meimand, S. Mukhopadhyay and K. Roy, "Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits," Custom Integrated Circuits Conference, pp. 17--20, 2004.
• 19: J. Wu, "CMOS transistor design challenges for mobile and digital consumer applications," International Conference on Solid-State and Integrated Circuits Technology, vol. 1, pp. 90--95, 2004.
• 20: A. A. Abu-Dayya and N. C. Beaulieu, "Comparison of methods of computing correlated lognormal sum distributions and outages for digital wireless applications," IEEE 44^th Vehicular Technology Conference, vol. 1, pp. 175--179, 1994.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance

Keywords:
leakage, process variation, random dopant fluctuation