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Trusted design in FPGAs
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 44th annual Design Automation Conference table of contents
San Diego, California
SESSION: Trusted hardware table of contents
Pages: 5 - 8  
Year of Publication: 2007
ISBN ~ ISSN:0738-100X , 978-1-59593-627-1
Author
Steve Trimberger  Xilinx, San Jose, CA
Sponsors
: The EDA Consortium
: IEEE/CASS/CANDE/CEDA
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 18,   Downloads (12 Months): 89,   Citation Count: 8
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ABSTRACT

Using FPGAs, a designer can separate the design process from the manufacturing flow. Therefore, the owner of a sensitive design need not expose the design to possible theft and tampering during its manufacture, dramatically simplifying the process of assuring trust in that design. Modern FPGAs include bitstream security features that turn the fielded design trust problem into an information security problem, with well-known cryptographic information security solutions. The generic nature of the FPGA base array allows the validation expense to be amortized over all designs targeted to that base array. Even the task of checking design tools is simplified by using non-destructive checks of the FPGA design.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Jones, L., "Single Event Upset (SEU) Detection and Correction Using Virtex-4 Devices", Xilinx Application Note #714, 2007, http://www.xilinx.com/bvdocs/appnotes/xapp714.pdf
 
2
Xilinx Virtex-4 Configuration Users Guide, v1.5, UG 071 2007, http://www.xilinx.com/bvdocs/userguides/ug071.pdf
3
 
4
Bennett, D., Private communication.
 
5
Wollinger, T. and Parr, C. "How Secure are FPGAs in Cryptographic Applications", 13th International Conference on Field Programmable Logic and Applications, FPL 2003, P. Y. K. Cheung, G. A. Constantinides, J. T. de Sousa, eds., LNCS 2887, Springer, 2003.
 
6
Feng, J. and Seely, J. A., "Design Security with Waveforms", http://www.altera.com/literature/cp/cp_sdr_design_security.pdf
 
7
Lesea, A., "IP Security in FPGAs", Xilinx http://direct.xilinx.com/bvdocs/whitepapers/wp261.pdf
 
8
Teliknepalli, A., "Is Your FPGA Design Secure?", XCell Journal, 2003, http://www.xilinx.com/publications/xcellonline/xcell_47/xc_pdf/xc_secure47.pdf
 
9
Baetoniu, C. and Sheth S., "FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure EEPROMs", Xilinx Application Note XAPP 780, Xilinx 2005.
 
10
Trimberger, S., FPGA Technology, Kluwer Academic Press, 1994.
 
11
Trimberger, S. "Method and apparatus for protecting proprietary configuration data for programmable logic devices", US Patent 6654889, 2003.
 
12
Schneier, B., Applied Cryptography Second Edition, Wiley, 1996.

CITED BY  8