A destructive evolutionary process: a pilot implementation

ABSTRACT

This paper describes the application of evolutionary search to the problem of Flash memory wear-out. The operating parameters of Flash memory are notoriously difficult to determine, as the optimal values vary from batch to batch. These parameters are usually established by an expensive, once off process of manual destructive testing at design time. Testing on individual batches is normally not feasible. We establish the viability of a platform that performs destructive experimentation on hard silicon, using a Genetic Algorithm to automatically discover optimal operating parameter settings. The results demonstrate a minimum average life extension of between 250% and 350% over the factory set read write and erase conditions with a maximum life extension exhibited of 700% for cells within the same device. It was necessary to build specialized hardware to perform the repetitive testing required by the GA, here we describe this hardware and demonstrate how the lessons learned in this pilot study will allow us to proceed with a more complex parallel evaluation platform, which will facilitate a larger problem space, larger population size and diversity of search techniques, facilitating the near no cost life extension of a split-gate Flash memory device.

REFERENCES

• 1: Aritome, S. Shirota, R. Hemink, G. Endoh, T. and Masuoka, F. "Reliability issues of Flash memory cells," Proc. IEEE, pp. 776--788, 1993.
• 2: Bhattacharya,s.,et al., "Improved Performance and Reliability of split gate Source side Injected flash memory cells, IEDM tech digest pp 339--342 1996
• 3: Chung, S. Cherng-Ming Yih, Shui-Ming Cheng, Mong-Song Liang "A New Technique for Hot Carrier Reliability Evaluations of Flash Memory Cell After Long-Term Program/Erase Cycles," IEEE Transactions On Electron Devices, Vol. 46, No. 9, September 1999.
• 4: Fitzpatrick, J. Michael JmfυVuse.Vanderbilt.Edu) John J. Grefenstette + GrefenstetteυVuse. Vanderbilt.Edu) Genetic Algorithms in Noisy Environments Computer Science Department, Vanderbilt University, Nashville, Tennessee 37235
• 5: Stephanie Forrest , Melanie Mitchell, What Makes a Problem Hard for a Genetic Algorithm? Some Anomalous Results and Their Explanation, Machine Learning, v.13 n.2-3, p.285-319, Nov./Dec. 1993 [doi>10.1007/BF00993046]
• 6: Fowler, R. H., and Nordheim, L.,"Electron Emmission in Intense Electric Fields," Proceedings of the Royal Society of london, vol. A119, pp. 172--81, 1928.
• 7: J Grefenstette, Optimization of control parameters for genetic algorithms, IEEE Transactions on Systems, Man and Cybernetics, v.16 n.1, p.122-128, Jan./Feb. 1986 [doi>10.1109/TSMC.1986.289288]
• 8: David E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1989
• 9: Haddad, S. Chang, S. Swaminathan, and J. Lien, "Degradation due to hole trapping in flash memory cells," IEEE Electron Device Lett., vol. 10, pp. 1 17--119, Mar. 1989.
• 10: Haddad, S. Chang, S. Wang, A. J. Bustillo, J. Lien, T. Montalvo, and M. Van Buskirk, "An investigation of erase-mode dependent hole trapping in Flash EEPROM memory cell," IEEE Electron Device Lett., vol. 11, pp. 514--516, 1990.
• 11: IEEE Std 1005--1998. "IEEE Standard Definitions And Characterization Of Floating Gate Semiconductor Arrays," New York: The Institute of Electrical and Electronic Engineers, Inc.
• 12: George F. Luger, Artificial Intelligence: Structures and Strategies for Complex Problem Solving, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 2001
• 13: Mohammad Gh. Mohammad , Kewal K. Saluja , Alex Yap, Testing Flash Memories, Proceedings of the 13th International Conference on VLSI Design, p.406, January 04-07, 2000
• 14: Pavan, P. Bez, R. Olivo, P. and E. Zanomi. Flash memory cells-An overview. Proc. IEEE, 85(8);1248--1271, Aug. 1997.
• 15: Colin R. Reeves, Using Genetic Algorithms with Small Populations, Proceedings of the 5th International Conference on Genetic Algorithms, p.92-99, June 01, 1993
• 16: Sakui, K. Ohuchi, and F. Masuoka, "Extended data retention characteristics after more than 10' write and erase cycles in EEPROMs," in IEEE IRPS 1990, pp. 259--264.
• 17: Silicon Storage Technology, Inc "Technical Comparison of Floating Gate Reprogrammable Nonvolatile Memories" Silicon Storage Technology, Inc. 1171 Sonora Court, Sunnyvale, www.ssti.com
• 18: Tam, S., et al., "Lucky Electron Model of Channel Hot-Electron Injection in MOSFETs", IEEE Transactions on Electron Devices, vol. ED-31, pp. 1116--1125, 1984.

INDEX TERMS

Primary Classification:
  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE
      I.2.8 Problem Solving, Control Methods, and Search

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories
          Subjects: Read-only memory (ROM)

General Terms:
Experimentation

Keywords:
experimentation, flash memory, reliability, silicon design