Scheduling for functional pipelining and loop winding

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Scheduling for functional pipelining and loop winding

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 764 - 769

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Cheng-Tsung Hwang	Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan 30043, R.O.C.
Yu-Chin Hsu	Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan 30043, R.O.C.
Youn-Long Lin	Department of Computer Science, Tsing Hua University, Hsinchu, Taiwan 30043, R.O.C.

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 28, Citation Count: 18

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M.C. McFarland, A.C. Parker and R. Camposano, "The High-Level Synthesis of Digital System", Proceedings of the IEEE, pp. 301-318, February 1990.
	2	N. Park and A.C. Parker, "Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications", IEEE Trans. on Computer-Aided Design, pp. 356-370, March 1988.
	3	David J. Mallon , Peter B. Denyer, A new approach to pipeline optimisation, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	4	P.G. Paulin, and J.P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's", IEEE Trans. on Computer-Aided Design, pp. 661-679, June 1989.
	5	Ki Soo Hwang, Albert E. Casavant, Ching-Tand Chang and Manuel A,d'Abreu, "Scheduling and Hardware sharing in pipelined data paths", Proc. of ICCAD-89, pp. 24-27, November 1989.
	6	E.M. Girczyc, "Loop Winging - a Data Flow Approach to Functional Pipelining", Proceedings of the IEEE ISCAS, pp 382-385, May 1987.
	7	Roni Potasman , Joseph Lis , Alexandru Nicolau , Daniel Gajski, Percolation based synthesis, Proceedings of the 27th ACM/IEEE conference on Design automation, p.444-449, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123333]
	8	A. Aiken , A. Nicolau, Optimal loop parallelization, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.308-317, June 20-24, 1988, Atlanta, Georgia, United States
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	10	G. Goossens, J. Rabaey, J. Vandewalle, and H. De Man, "An efficient Micro-code Compiler for Application Specific DSP Processors", 1EEE Trans. on Computer- Aided Design, pp. 925-937, June 1990.
	11	Ronald Gary Cytron, Compile-time scheduling and optimization for asynchronous machines (multiprocessor, compiler, parallel processing), 1984
	12	M. S. Lain, "A Systolic Array Optimizing Compiler," Ph.D. thesis, Univ. of Carnegie Mellon, 1989.
	13	Cheng-Tsung Hwang , Yu-Chin Hsu , Youn-Long Lin, Optimum and heuristic data path scheduling under resource constraints, Proceedings of the 27th ACM/IEEE conference on Design automation, p.65-70, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123228]
	14	F.S. Tsai and Y. C. Hsu, "DataPath Construction and Refinement," Proc. of ICCAD-90.
	15	S. Y. Kung , Thomas Kailath , Harper J. Whitehouse, VLSI and Modern Signal Processing, Prentice Hall Professional Technical Reference, 1984

CITED BY 18

	Laurence Goodby , Alex Orailoğlu , Paul M. Chau, Microarchitectural synthesis of performance-constrained, low-power VLSI designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.1, p.122-136, January 2002
	Yuan-Long Jeang , Yu-Chin Hsu , Jhing-Fa Wang , Jau-Yien Lee, High throughput pipelined data path synthesis by conserving the regularity of nested loops, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.450-453, November 07-11, 1993, Santa Clara, California, United States
	Ing-Jer Huang, Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.1, p.93-121, Jan. 2001
	M. Nourani , C. Papachristou, Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems, Proceedings of the 29th ACM/IEEE conference on Design automation, p.99-105, June 08-12, 1992, Anaheim, California, United States
	Haigeng Wang , Nikil Dutt , Alexandru Nicolau, Harmonic scheduling of linear recurrences for digital filter design, Proceedings of the conference on European design automation, p.396-401, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Haigeng Wang , Nikil Dutt , Alexandru Nicolau , Kai-Yeung Sunny Siu, High-level synthesis of scalable architectures for IIR filters using multichip modules, Proceedings of the 30th international conference on Design automation, p.336-342, June 14-18, 1993, Dallas, Texas, United States
	Ing-Jer Huang , Alvin M. Despain, Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.594-599, November 07-11, 1993, Santa Clara, California, United States
	Tsing-Fa Lee , Allen C.-H. Wu , Daniel D. Gajski , Youn-Long Lin, An effective methodology for functional pipelining, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.230-233, November 1992, Santa Clara, California, United States
	Richard J. Cloutier , Donald E. Thomas, Synthesis of pipelined instruction set processors, Proceedings of the 30th international conference on Design automation, p.583-588, June 14-18, 1993, Dallas, Texas, United States
	Albert E. Casavant, MIST—a design aid for programmable pipelined processors, Proceedings of the 31st annual conference on Design automation, p.532-536, June 06-10, 1994, San Diego, California, United States
	Daehong Kim , Kiyoung Choi, Power-conscious high level synthesis using loop folding, Proceedings of the 34th annual conference on Design automation, p.441-445, June 09-13, 1997, Anaheim, California, United States
	Daehong Kim , Dongwan Shin , Kiyoung Choi, Low power pipelining of linear systems: a common operand centric approach, Proceedings of the 2001 international symposium on Low power electronics and design, p.225-230, August 2001, Huntington Beach, California, United States
	Ramesh Karri , Alex Orailoğlu, ALPS: an algorithm for pipeline data path synthesis, Proceedings of the 24th annual international symposium on Microarchitecture, p.124-132, September 1991, Albuquerque, New Mexico, Puerto Rico
	François R. Boyer , El Mostapha Aboulhamid , Yvon Savaria , Michel Boyer, Optimal design of synchronous circuits using software pipelining techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.4, p.516-532, October 2001
	Ing-Jer Huang , Alvin M. Despain, An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors, Proceedings of the 26th annual international symposium on Microarchitecture, p.236-246, December 01-03, 1993, Austin, Texas, United States
	Maria-Cristina V. Marinescu , Martin Rinard, High-level automatic pipelining for sequential circuits, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Y.-H. Hung , A. C. Parker, High-level synthesis with pin constraints for multiple-chip designs, Proceedings of the 29th ACM/IEEE conference on Design automation, p.231-234, June 08-12, 1992, Anaheim, California, United States
	Minjoong Rim , Rajiv Jain, Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications, IEEE Transactions on Parallel and Distributed Systems, v.7 n.4, p.399-410, April 1996