| Fast and near optimal scheduling in automatic data path synthesis |
| Full text |
Pdf
(704 KB)
|
| Source
|
Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 28th ACM/IEEE Design Automation Conference
table of contents
San Francisco, California, United States
Pages: 680 - 685
Year of Publication: 1991
ISBN:0-89791-395-7
|
|
Authors
|
|
In-Cheol Park
|
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Seoul, 130-650, Korea
|
|
Chong-Min Kyung
|
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Seoul, 130-650, Korea
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 9, Downloads (12 Months): 18, Citation Count: 3
|
|
|
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
C. Tseng and D.P. Siewiorek, "Automated synthesis of data paths in digital systems," IEEE Trans. Computer-Aided Design, vol. CAD-5, pp.379-395, July 1986.
|
| |
2
|
|
| |
3
|
H. Trickey, ~Flamel: A high-level hardware compiler," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 259-269, Max. 1987.
|
| |
4
|
|
 |
5
|
|
| |
6
|
|
| |
7
|
J-H. Lee, Y-C. Hsu, and Y-L. Lin, "A new integer linear programming formulation for the scheduling program in data path synthesis," Proc. ICCAD-89, pp. 20-23, 1989.
|
| |
8
|
B.W. Kernighan and S. Lin, "An efficient heuristic procedure for partitioning graphs," Bell Syst. Tech. J., vol 49, no. 2, pp. 291-308, 1970.
|
| |
9
|
|
| |
10
|
|
| |
11
|
|
CITED BY 3
|
|
|
|
|
Ying Yi , Ioannis Nousias , Mark Milward , Sami Khawam , Tughrul Arslan , Iain Lindsay, System-level scheduling on instruction cell based reconfigurable systems, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
|
|
|
Kevin Fan , Manjunath Kudlur , Hyunchul Park , Scott Mahlke, Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.219-232, November 12-16, 2005, Barcelona, Spain
|
|