3D scheduling

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3D scheduling: high-level synthesis with floorplanning

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 668 - 673

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Jen-Pin Weng	Department of Electrical Engineering Systems, University of Southern California, University Park, Los Angeles, CA
Alice C. Parker	Department of Electrical Engineering Systems, University of Southern California, University Park, Los Angeles, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 16, Downloads (12 Months): 43, Citation Count: 24

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Alice C. Parker , Jorge T. Pizarro , Mitch Mlinar, MAHA: a program for datapath synthesis, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.461-466, July 1986, Las Vegas, Nevada, United States
	2	T. Sakurai, "Approximation of Wiring Delay in MOS- FET LSI', IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 4, pp. 418-426, Aug. 1983.
	3	Alice C. Parker , Pravil Gupta , Agha Hussain, The effects of physical design characteristics on the area-performance tradeoff curve, Proceedings of the 28th conference on ACM/IEEE design automation, p.530-534, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127727]
	4	David W. Knapp, "Feedback-Driven Datapath Optimization in Fasolt", Proc. of the 27th Design Automation Conference, Jul. 1990.
	5	Michael C. McFarland, Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.474-480, July 1986, Las Vegas, Nevada, United States
	6	P. R. Suaris and G. Kedem, "A Quadrisection-Based Combined Place and Route Scheme for Standard Cells", IEEE Trans. on Computer-Aided Design, Vol. 8, No. 3, Mar. 1989.
	7	E. Girczyc, "Automatic Generation of Microseqenced Data Paths to Realize ADA Circuit Descriptions", PhD thesis, Carleton University, Jul. 1984.
	8	F. Brewer and D. Gajski, "Chippe: A System for Constraint Driven Behavioral Synthesis , IEEE Trans. on Computer-Aided Design, vol. 9, no. 7, pp. 681-695, Jul. 1990.
	9	Wilm E. Donath , Reini J. Norman , Bhuwan K. Agrawal , Stephen E. Bello , Sang Yong Han , Jerome M. Kurtzberg , Paul Lowy , Roger I. McMillan, Timing driven placement using complete path delays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.84-89, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123232]
	10	A. E. Dunlop , V. D. Agrawal , D. N. Deutsch , M. F. Jukl , P. Kozak , M. Wiesel, Chip layout optimization using critical path weighting, Proceedings of the 21st conference on Design automation, p.133-136, June 25-27, 1984, Albuquerque, New Mexico, United States
	11	Ting-chi Wang , D. F. Wong, An optimal algorithm for floorplan area optimization, Proceedings of the 27th ACM/IEEE conference on Design automation, p.180-186, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123253]
	12	Ting-chi Wang , D. F. Wong, An optimal algorithm for floorplan area optimization, Proceedings of the 27th ACM/IEEE conference on Design automation, p.180-186, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123253]
	13	Y. Lai and S. Leinwand. Algorithms for Floorplan Design via Rectangluar Dualization. 1EEE Trans. on Computer-Aided Design, Dec. 1988.

CITED BY 24

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	Mehrdad Nourani , Christos Papachristou, A layout estimation algorithm for RTL datapaths, Proceedings of the 30th international conference on Design automation, p.285-291, June 14-18, 1993, Dallas, Texas, United States
	Jianwen Zhu , Daniel D. Gajski, Soft scheduling in high level synthesis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.219-224, June 21-25, 1999, New Orleans, Louisiana, United States
	M. Xu , F. J. Kurdahi, Layout-driven high level synthesis for FPGA based architectures, Proceedings of the conference on Design, automation and test in Europe, p.446-450, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Hyuk-Jae Jang , Barry M. Pangrle, A grid-based approach for connectivity binding with geometric costs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.94-99, November 07-11, 1993, Santa Clara, California, United States
	Mehrdad Nourani , Christos A. Papachristou, False path exclusion in delay analysis of RTL structures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.30-43, 2/1/2002
	Min Xu , Fadi J. Kurdahi, Layout-driven RTL binding techniques for high-level synthesis using accurate estimators, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.4, p.312-343, Oct. 1997
	Champaka Ramachandran , Fadi J. Kurdahi, Combined topological and functionality based delay estimation using a layout-driven approach for high level applications, Proceedings of the conference on European design automation, p.72-78, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	C. Papachristou , M. Nourani, False path exclusion in delay analysis of RTL-based datapath-controller designs, Proceedings of the conference on European design automation, p.336-341, September 1996, Geneva, Switzerland
	Vasily G. Moshnyaga , Hiroshi Mori , Hidetoshi Onodera , Keikichi Tamaru, Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.100-103, November 07-11, 1993, Santa Clara, California, United States
	Doron Mintz , Carlos Dangelo, Timing estimation for behavioral descriptions, Proceedings of the 7th international symposium on High-level synthesis, p.42-47, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
	Christos Papachristou , Haidar Harmanani , Mehrdad Nourani, An approach for redesigning in data path synthesis, Proceedings of the 30th international conference on Design automation, p.419-423, June 14-18, 1993, Dallas, Texas, United States
	Daehong Kim , Jinyong Jung , Sunghyun Lee , Jinhwan Jeon , Kiyoung Choi, Behavior-to-placed RTL synthesis with performance-driven placement, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Junhyung Um , Jae-hoon Kim , Taewhan Kim, Layout-driven resource sharing in high-level synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.614-618, November 10-14, 2002, San Jose, California
	Shantanu Tarafdar , Miriam Leeser , Zixin Yin, Integrating floorplanning in data-transfer based high-level synthesis, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.412-417, November 08-12, 1998, San Jose, California, United States
	Kyumyung Choi , Steven P. Levitan, A flexible datapath allocation method for architectural synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.4, p.376-404, Oct. 1999
	Yung-Ming Fang , D. F. Wong, Simultaneous functional-unit binding and floorplanning, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.317-321, November 06-10, 1994, San Jose, California, United States
	Zhenyu (Peter) Gu , Jia Wang , Robert P. Dick , Hai Zhou, Incremental exploration of the combined physical and behavioral design space, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Lin Zhong , Niraj K. Jha, Interconnect-aware high-level synthesis for low power, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.110-117, November 10-14, 2002, San Jose, California
	Taemin Kim , Xun Liu, Compatibility path based binding algorithm for interconnect reduction in high level synthesis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Junhyung Um , Taewhan Kim, Resource Sharing Combined with Layout Effects in High-Level Synthesis, Journal of VLSI Signal Processing Systems, v.44 n.3, p.231-243, September 2006
	Jason Cong , Yiping Fan , Guoling Han , Xun Yang , Zhiru Zhang, Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.536, November 09-13, 2003
	A. Stammermann , D. Helms , M. Schulte , A. Schulz , W. Nebel, Binding, Allocation and Floorplanning in Low Power High-Level Synthesis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.544, November 09-13, 2003
	Rajarshi Mukherjee , Seda Ogrenci Memik, An integrated approach to thermal management in high-level synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.11, p.1165-1174, November 2006