| Transition density, a stochastic measure of activity in digital circuits |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 28th ACM/IEEE Design Automation Conference
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San Francisco, California, United States
Pages: 644 - 649
Year of Publication: 1991
ISBN:0-89791-395-7
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Author
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Farid N. Najm
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Semiconductor Process & Design Center, Texas Instruments Inc., MS 369, Dallas, Texas
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Downloads (6 Weeks): 5, Downloads (12 Months): 32, Citation Count: 68
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/123186.123222]
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F. N. Sajm, R. Surch, P. Yang, and I. N. Hajj, UP~ob~bili~i~ ~imul~tio~ for ~eliability analy~i~ of CMOS VLSI circuits," IEEE Trans. Computer- Aided Design, pp. 439-450, April 1990 (Errata in July 1990).
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CITED BY 68
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Mitsuhisa Ohnishi , Akihisa Yamada , Hiroaki Noda , Takashi Kambe, A method of redundant clocking detection and power reduction at RT level design, Proceedings of the 1997 international symposium on Low power electronics and design, p.131-136, August 18-20, 1997, Monterey, California, United States
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Tan-Li Chou , Kaushik Roy , Sharat Prasad, Estimation of circuit activity considering signal correlations and simultaneous switching, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.300-303, November 06-10, 1994, San Jose, California, United States
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Richard Burch , Farid Najm , Ping Yang , Timothy Trick, McPOWER: a Monte Carlo approach to power estimation, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.90-97, November 1992, Santa Clara, California, United States
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Unni Narayanan , Peichen Pan , C. L. Liu, Low power logic synthesis under a general delay model, Proceedings of the 1998 international symposium on Low power electronics and design, p.209-214, August 10-12, 1998, Monterey, California, United States
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Masanori Hashimoto , Hidetoshi Onodera , Keikichi Tamaru, A practical gate resizing technique considering glitch reduction for low power design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.446-451, June 21-25, 1999, New Orleans, Louisiana, United States
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Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Technology decomposition and mapping targeting low power dissipation, Proceedings of the 30th international conference on Design automation, p.68-73, June 14-18, 1993, Dallas, Texas, United States
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Unni Narayanan , Hon Wai Leong , Ki-seok Chung , C. L. Liu, Low power multiplexer decomposition, Proceedings of the 1997 international symposium on Low power electronics and design, p.269-274, August 18-20, 1997, Monterey, California, United States
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Masanori Hashimoto , Hidetoshi Onodera , Keikichi Tamaru, A power optimization method considering glitch reduction by gate sizing, Proceedings of the 1998 international symposium on Low power electronics and design, p.221-226, August 10-12, 1998, Monterey, California, United States
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Taku Uchino , Fumihiro Minami , Takashi Mitsuhashi , Nobuyuki Goto, Switching activity analysis using Boolean approximation method, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.20-25, November 05-09, 1995, San Jose, California, United States
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Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
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Vivek Tiwari , Pranav Ashar , Sharad Malik, Technology mapping for lower power, Proceedings of the 30th international conference on Design automation, p.74-79, June 14-18, 1993, Dallas, Texas, United States
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Vivek Tiwari , Sharad Malik , Pranav Ashar, Guarded evaluation: pushing power management to logic synthesis/design, Proceedings of the 1995 international symposium on Low power design, p.221-226, April 23-26, 1995, Dana Point, California, United States
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Radu Marculescu , Diana Marculescu , Massoud Pedram, Switching activity analysis considering spatiotemporal correlations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.294-299, November 06-10, 1994, San Jose, California, United States
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A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
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Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States
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José Monteiro , Srinivas Devadas , Abhijit Ghosh, Retiming sequential circuits for low power, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.398-402, November 07-11, 1993, Santa Clara, California, United States
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Charlie X. Huang , Bill Zhang , An-Chang Deng , Burkhard Swirski, The design and implementation of PowerMill, Proceedings of the 1995 international symposium on Low power design, p.105-110, April 23-26, 1995, Dana Point, California, United States
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Zhanping Chen , Kaushik Roy , Tan-Li Chou, Power sensitivity—a new method to estimate power dissipation considering uncertain specifications of primary inputs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.40-44, November 09-13, 1997, San Jose, California, United States
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Michel R. C. M. Berkelaar , Pim H. W. Buurman , Jochen A. G. Jess, Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.474-480, November 06-10, 1994, San Jose, California, United States
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Pankaj Pant , Vivek De , Abhijit Chatterjee, Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks, Proceedings of the 34th annual conference on Design automation, p.403-408, June 09-13, 1997, Anaheim, California, United States
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Farid N. Najm, Feedback, correlation, and delay concerns in the power estimation of VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.612-617, June 12-16, 1995, San Francisco, California, United States
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Diana Marculescu , Radu Marculescu , Massoud Pedram, Stochastic sequential machine synthesis targeting constrained sequence generation, Proceedings of the 33rd annual conference on Design automation, p.696-701, June 03-07, 1996, Las Vegas, Nevada, United States
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Mazhar Alidina , José Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios Papaefthymiou, Precomputation-based sequential logic optimization for low power, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.74-81, November 06-10, 1994, San Jose, California, United States
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Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
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Zhanping Chen , Mark Johnson , Liqiong Wei , Kaushik Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, Proceedings of the 1998 international symposium on Low power electronics and design, p.239-244, August 10-12, 1998, Monterey, California, United States
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T. Uchino , F. Minami , M. Murakata , T. Mitsuhashi, Switching activity analysis for sequential circuits using Boolean approximation method, Proceedings of the 1996 international symposium on Low power electronics and design, p.79-84, August 12-14, 1996, Monterey, California, United States
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R. Iris Bahar , Gary D. Hachtel , Enrico Macii , Fabio Somenzi, A symbolic method to reduce power consumption of circuits containing false paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.368-371, November 06-10, 1994, San Jose, California, United States
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Gary D. Hachtel , Mariano Hermida , Abelardo Pardo , Massimo Poncino , Fabio Somenzi, Re-encoding sequential circuits to reduce power dissipation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.70-73, November 06-10, 1994, San Jose, California, United States
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David Ihsin Cheng , Kwang-Ting Cheng , Deborah C. Wang , Malgorzata Marek-Sadowska, A new hybrid methodology for power estimation, Proceedings of the 33rd annual conference on Design automation, p.439-444, June 03-07, 1996, Las Vegas, Nevada, United States
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José C. Costa , José C. Monteiro , Srinivas Devadas, Switching activity estimation using limited depth reconvergent path analysis, Proceedings of the 1997 international symposium on Low power electronics and design, p.184-189, August 18-20, 1997, Monterey, California, United States
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