Transition density, a stochastic measure of activity in digital circuits

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Transition density, a stochastic measure of activity in digital circuits

Full text

Pdf (623 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 644 - 649

Year of Publication: 1991

ISBN:0-89791-395-7

Author

Farid N. Najm

Semiconductor Process & Design Center, Texas Instruments Inc., MS 369, Dallas, Texas

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 33, Citation Count: 68

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/127601.127744 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. Papoulis, Probability, Random Variables, and Stochastic Processes, 2nd Edition. New York, NY: McGraw-Hill Book Co., 1984.
	2	E. Par~en, Stochastic Processes, San Francisco, CA: Holden-Day Inc., 1962.
	3	D. R. Cox and H. D. Miller, The Theory of Stochastic Processes, New York" John Wiley & Sons Inc., 1968.
	4	K. P. Parker and E. :I. McCluskey, "Probabilistic treatment of general combinational networks," IEEE Trans. Computers, pp. 668-670, June 1975.
	5	S. C. Seth, L. Pan, and V. D. Agrawal, "PRE- DICT- probabilistic estimation of digital circuit testability," IEEE 15th Annual international Symposium or~ Fault-Tolerant Computing, Ann Arbor, MI, pp. 220-225, June 1985.
	6	J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability," IEEE Trans. Computers, pp. 79-90, January 1984.
	7	G. Markowsky, Bounding signal probabilities in combinational circuits, IEEE Transactions on Computers, v.36 n.10, p.1247-1251, Oct. 1987 [doi>10.1109/TC.1987.1676866]
	8	S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricc6, "Estimate of signal probability in combinational logic networks," 1989 IEEE European Test Conference, pp. 132-138, 1989.
	9	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	10	Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123222]
	11	F. N. Sajm, R. Surch, P. Yang, and I. N. Hajj, UP~ob~bili~i~ ~imul~tio~ for ~eliability analy~i~ of CMOS VLSI circuits," IEEE Trans. Computer- Aided Design, pp. 439-450, April 1990 (Errata in July 1990).

CITED BY 68

	Mitsuhisa Ohnishi , Akihisa Yamada , Hiroaki Noda , Takashi Kambe, A method of redundant clocking detection and power reduction at RT level design, Proceedings of the 1997 international symposium on Low power electronics and design, p.131-136, August 18-20, 1997, Monterey, California, United States
	Tan-Li Chou , Kaushik Roy , Sharat Prasad, Estimation of circuit activity considering signal correlations and simultaneous switching, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.300-303, November 06-10, 1994, San Jose, California, United States
	José Monteiro , Srinivas Devadas, Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs, Proceedings of the 1995 international symposium on Low power design, p.33-38, April 23-26, 1995, Dana Point, California, United States
	Richard Burch , Farid Najm , Ping Yang , Timothy Trick, McPOWER: a Monte Carlo approach to power estimation, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.90-97, November 1992, Santa Clara, California, United States
	E. Musoll , J. Cortadella, High-level synthesis techniques for reducing the activity of functional units, Proceedings of the 1995 international symposium on Low power design, p.99-104, April 23-26, 1995, Dana Point, California, United States
	Unni Narayanan , Peichen Pan , C. L. Liu, Low power logic synthesis under a general delay model, Proceedings of the 1998 international symposium on Low power electronics and design, p.209-214, August 10-12, 1998, Monterey, California, United States
	Masanori Hashimoto , Hidetoshi Onodera , Keikichi Tamaru, A practical gate resizing technique considering glitch reduction for low power design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.446-451, June 21-25, 1999, New Orleans, Louisiana, United States
	S. C. Prasad , K. Roy, Transistor reordering for power minimization under delay constraint, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.280-300, April 1996
	Glenn Holt , Akhilesh Tyagi, Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis, Proceedings of the 1997 international symposium on Physical design, p.48-53, April 14-16, 1997, Napa Valley, California, United States
	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Technology decomposition and mapping targeting low power dissipation, Proceedings of the 30th international conference on Design automation, p.68-73, June 14-18, 1993, Dallas, Texas, United States
	Unni Narayanan , Hon Wai Leong , Ki-seok Chung , C. L. Liu, Low power multiplexer decomposition, Proceedings of the 1997 international symposium on Low power electronics and design, p.269-274, August 18-20, 1997, Monterey, California, United States
	Masanori Hashimoto , Hidetoshi Onodera , Keikichi Tamaru, A power optimization method considering glitch reduction by gate sizing, Proceedings of the 1998 international symposium on Low power electronics and design, p.221-226, August 10-12, 1998, Monterey, California, United States
	Aurobindo Dasgupta , Ramesh Karri, Simultaneous scheduling and binding for power minimization during microarchitecture synthesis, Proceedings of the 1995 international symposium on Low power design, p.69-74, April 23-26, 1995, Dana Point, California, United States
	Sachin S. Sapatnekar , Weitong Chuang, Power-delay optimizations in gate sizing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.1, p.98-114, Jan. 2000
	Taku Uchino , Fumihiro Minami , Takashi Mitsuhashi , Nobuyuki Goto, Switching activity analysis using Boolean approximation method, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.20-25, November 05-09, 1995, San Jose, California, United States
	Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
	R. Iris Bahar , Fabio Somenzi, Boolean techniques for low power driven re-synthesis, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.428-432, November 05-09, 1995, San Jose, California, United States
	Olivier Coudert , Ramsey Haddad, Integrated resynthesis for low power, Proceedings of the 1996 international symposium on Low power electronics and design, p.169-174, August 12-14, 1996, Monterey, California, United States
	Vivek Tiwari , Pranav Ashar , Sharad Malik, Technology mapping for lower power, Proceedings of the 30th international conference on Design automation, p.74-79, June 14-18, 1993, Dallas, Texas, United States
	Yen-Jen Chang , Shanq-Jang Ruan , Feipei Lai, Sentry tag: an efficient filter scheme for low power cache, Australian Computer Science Communications, v.24 n.3, p.135-140, January-February 2002
	Vivek Tiwari , Sharad Malik , Pranav Ashar, Guarded evaluation: pushing power management to logic synthesis/design, Proceedings of the 1995 international symposium on Low power design, p.221-226, April 23-26, 1995, Dana Point, California, United States
	Radu Marculescu , Diana Marculescu , Massoud Pedram, Switching activity analysis considering spatiotemporal correlations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.294-299, November 06-10, 1994, San Jose, California, United States
	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
	P. Schneider , S. Krishnamoorthy, Effects of correlations on accuracy of power analysis—an experimental study, Proceedings of the 1996 international symposium on Low power electronics and design, p.113-116, August 12-14, 1996, Monterey, California, United States
	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States
	Mahesh Mamidipaka , Dan Hirschberg , Nikil Dutt, Low power address encoding using self-organizing lists, Proceedings of the 2001 international symposium on Low power electronics and design, p.188-193, August 2001, Huntington Beach, California, United States
	José Monteiro , Srinivas Devadas , Abhijit Ghosh, Retiming sequential circuits for low power, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.398-402, November 07-11, 1993, Santa Clara, California, United States
	Charlie X. Huang , Bill Zhang , An-Chang Deng , Burkhard Swirski, The design and implementation of PowerMill, Proceedings of the 1995 international symposium on Low power design, p.105-110, April 23-26, 1995, Dana Point, California, United States
	Aurobindo Dasgupta , Ramesh Karri, Electromigration reliability enhancement via bus activity distribution, Proceedings of the 33rd annual conference on Design automation, p.353-356, June 03-07, 1996, Las Vegas, Nevada, United States
	Zhanping Chen , Kaushik Roy , Tan-Li Chou, Power sensitivity—a new method to estimate power dissipation considering uncertain specifications of primary inputs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.40-44, November 09-13, 1997, San Jose, California, United States
	Guiseppe Bernacchia , Marios C. Papaefthymiou, Analytical macromodeling for high-level power estimation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.280-283, November 07-11, 1999, San Jose, California, United States
	Diana Marculescu , Radu Marculescu , Massoud Pedram, Stochastic sequential machine synthesis with application to constrained sequence generation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.658-681, July 2000
	Michel R. C. M. Berkelaar , Pim H. W. Buurman , Jochen A. G. Jess, Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.474-480, November 06-10, 1994, San Jose, California, United States
	Pankaj Pant , Vivek De , Abhijit Chatterjee, Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks, Proceedings of the 34th annual conference on Design automation, p.403-408, June 09-13, 1997, Anaheim, California, United States
	Farid N. Najm, Feedback, correlation, and delay concerns in the power estimation of VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.612-617, June 12-16, 1995, San Francisco, California, United States
	Peter H. Schneider , Kurt J. Antreich , Ulf Schlichtmann, A new power estimation technique with application to decomposition of Boolean functions for low power, Proceedings of the conference on European design automation, p.388-393, September 19-23, 1994, Grenoble, France
	Christopher K. Lennard , A. Richard Newton, An estimation technique to guide low power resynthesis algorithms, Proceedings of the 1995 international symposium on Low power design, p.227-232, April 23-26, 1995, Dana Point, California, United States
	Diana Marculescu , Radu Marculescu , Massoud Pedram, Stochastic sequential machine synthesis targeting constrained sequence generation, Proceedings of the 33rd annual conference on Design automation, p.696-701, June 03-07, 1996, Las Vegas, Nevada, United States
	Jyh-Mou Tseng , Jing-Yang Jou, Two-level logic minimization for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.52-69, Jan. 1999
	Yu-Lung Hsu , Sying-Jyan Wang, Retiming-based logic synthesis for low-power, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Mazhar Alidina , José Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios Papaefthymiou, Precomputation-based sequential logic optimization for low power, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.74-81, November 06-10, 1994, San Jose, California, United States
	Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
	Zhanping Chen , Mark Johnson , Liqiong Wei , Kaushik Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, Proceedings of the 1998 international symposium on Low power electronics and design, p.239-244, August 10-12, 1998, Monterey, California, United States
	T. Uchino , F. Minami , M. Murakata , T. Mitsuhashi, Switching activity analysis for sequential circuits using Boolean approximation method, Proceedings of the 1996 international symposium on Low power electronics and design, p.79-84, August 12-14, 1996, Monterey, California, United States
	R. Iris Bahar , Gary D. Hachtel , Enrico Macii , Fabio Somenzi, A symbolic method to reduce power consumption of circuits containing false paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.368-371, November 06-10, 1994, San Jose, California, United States
	Sasan Iman , Massoud Pedram, Multi-level network optimization for low power, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.372-377, November 06-10, 1994, San Jose, California, United States
	Gary D. Hachtel , Mariano Hermida , Abelardo Pardo , Massimo Poncino , Fabio Somenzi, Re-encoding sequential circuits to reduce power dissipation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.70-73, November 06-10, 1994, San Jose, California, United States
	Huy T. Nguyen , Abhijit Chatterjee , Rabindra K. Roy, Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis, Journal of VLSI Signal Processing Systems, v.18 n.1, p.25-38, Jan. 1998
	Peter H. Schneider , Ulf Schlichtmann , Bernd Wurth, Fast Power Estimation of Large Circuits, IEEE Design & Test, v.13 n.1, p.70-78, March 1996
	Sungpack Hong , Taewhan Kim, Bus optimization for low-power data path synthesis based on network flow method, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Chun Gi Lyuh , Taewhan Kim , C. L. Liu, An integrated data path optimization for low power based on network flow method, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Ki-Seok Chung , Taewhan Kim , C. L. Liu, G-vector: A New Model for Glitch Analysis in Logic Circuits, Journal of VLSI Signal Processing Systems, v.27 n.3, p.235-251, March 1, 2001
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, High-level macro-modeling and estimation techniques for switching activity and power consumption, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.538-557, August 2003
	Sachin S. Sapatnekar , Weitong Chuang, Power vs. delay in gate sizing: conflicting objectives?, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.463-466, November 05-09, 1995, San Jose, California, United States
	Kaushik Roy , Sharat Prasad, Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effects, Proceedings of the conference on European design automation, p.136-141, September 19-23, 1994, Grenoble, France
	X. Liu , C. Papaefthymiou, A static power estimation methodolodgy for IP-based design, Proceedings of the conference on Design, automation and test in Europe, p.280-289, March 2001, Munich, Germany
	David Ihsin Cheng , Kwang-Ting Cheng , Deborah C. Wang , Malgorzata Marek-Sadowska, A new hybrid methodology for power estimation, Proceedings of the 33rd annual conference on Design automation, p.439-444, June 03-07, 1996, Las Vegas, Nevada, United States
	Mahesh N. Mamidipaka , Daniel S. Hirschberg , Nikil D. Dutt, Adaptive low-power address encoding techniques using self-organizing lists, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.827-834, October 2003
	José C. Costa , José C. Monteiro , Srinivas Devadas, Switching activity estimation using limited depth reconvergent path analysis, Proceedings of the 1997 international symposium on Low power electronics and design, p.184-189, August 18-20, 1997, Monterey, California, United States
	Yong-Jun Xu , Zu-Ying Luo , Xiao-Wei Li , Li-Jian Li , Xian-Long Hong, Leakage current estimation of CMOS circuit with stack effect, Journal of Computer Science and Technology, v.19 n.5, p.708-717, September 2004
	Hassan Hassan , Mohab Anis , Mohamed Elmasry, LAP: a logic activity packing methodology for leakage power-tolerant FPGAs, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Xun Liu , Marios C. Papaefthymiou, HyPE: hybrid power estimation for IP-based programmable systems, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Chun-Gi Lyuh , Taewhan Kim, High-level synthesis for low power based on network flow method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.364-375, June 2003
	Suresh Srinivasan , Prasanth Mangalagiri , Yuan Xie , N. Vijaykrishnan , Karthik Sarpatwari, FLAW: FPGA lifetime awareness, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	Bin Zhang , Wei-Shen Wang , Michael Orshansky, FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs, Proceedings of the 7th International Symposium on Quality Electronic Design, p.755-760, March 27-29, 2006
	Enric Musoll , Jordi Cortadella, Optimizing CMOS Circuits for Low Power Using Transistor Reordering, Proceedings of the 1996 European conference on Design and Test, p.219, March 11-14, 1996
	Ashish K. Singh , Michael Orshansky, Logic synthesis for reducing leakage power consumption under workload uncertainty, Proceedings of the 12th WSEAS international conference on Circuits, p.351-355, July 22-24, 2008, Heraklion, Greece