Placement for clock period minimization with multiple wave propagation

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Placement for clock period minimization with multiple wave propagation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 640 - 643

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Donald A. Joy	Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA
Maciej J. Ciesielski	Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 7, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Fis90	John P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, v.39 n.7, p.945-951, July 1990 [doi>10.1109/12.55696]
	Joy90	D. A. Joy, M. J. Ciesielski, "Clock Period Minimization in Standard Cell Layout", Int. Workshop on Layout Synthesis Proc. 1990, Microelectronics Center of North Carolina, pp.
	Joy91	D. A. Joy, M. J. Ciesielski, "Clock Period Minimization with Simultaneous Multiple Signal Propagation", Submitted to IEEE Trans. on Computer-Aided Design.
	Whi84	J. White, N. Weiner, D. Webber, K. Kundert, P. Moore, R. A. galeh, A. ganglovanni-Vincentelll, A. R. Newton, "Relax2.3 User's Guide" Dept. of EE and CS, University of California, Berkeley.

CITED BY 2

	William K. C. Lam , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Valid clocking in wavepipelined circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.518-525, November 1992, Santa Clara, California, United States
	Atsushi Takahashi , Kazunori Inoue , Yoji Kajitani, Clock-tree routing realizing a clock-schedule for semi-synchronous circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.260-265, November 09-13, 1997, San Jose, California, United States