Data-path synthesis using path analysis

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. C. McFarland, A. C. Parker, and R. Camposano, "The high-level synthesis of digital systems," Proceedings of the IEEE, pp. 301-318, February 1990.
	2	P. G. Paulin and J. P. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Transactwns on Computer-Azded Design, vol. CAD-8, pp. 661- 679, June 1989.
	3	C. J. Tseng and D. P. Siewiorek, "Automated synthesis of data paths in digital systems," IEEE Transactwns on Computer-Aided Design, vol. CAD-5, pp. 379-395, July 1986.
	4	L. J. Hafer and A. C. Parker, "A formal method for the specification, analysis, and design of register-transfer level digital logic," IEEE Transactions on Computer- Azded Deszgn, vol. CAD-2, pp. 4-18, January 1983.
	5	J. Lee, Y. Hsu, and Y. Lin, "A new integer linear programming formulation for the scheduling problem in data path synthesis," in Proceedings of the IEEE International Conference on Computer-Aided Design, IEEE, November 1989.
	6	Donald E. Thomas , Elizabeth D. Lagnese , John A. Nestor , Jayanth V. Rajan , Robert L. Blackburn , Robert A. Walker, Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, Norwell, MA, 1989
	7	Richard J. Cloutier , Donald E. Thomas, The combination of scheduling, allocation, and mapping in a single algorithm, Proceedings of the 27th ACM/IEEE conference on Design automation, p.71-76, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123230]
	8	Raul Compasano , Reinaldo A. Bergamaschi, Synthesis using path-based scheduling: algorithms and exercises, Proceedings of the 27th ACM/IEEE conference on Design automation, p.450-455, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123335]
	9	R. Camposano, "Path-based scheduling for synthesis," IEEE Transactions on Computer-Aided Design, vol. CAD-10, pp. 85-93, January 1991.
	10	G. J. Chaitin, M. A. Auslander, A. K. Chandra, J. Cocke, M. E. Hopkins, and P. W. Markstein, "Register allocation via coloring," Tech. Rep. Computer Science, RC 8395 (~36543), IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598, April 1980.
	11	Reinaldo A. Bergamaschi , Raul Camposano , Michael Payer, Area and performance optimizations in path-based scheduling, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	12	Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
	13	T. K. PhiIips, "New algorithms to color graphs and find maximum cliques," Tech. Rep. Computer Science, Research Report, IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598, 1990.
	14	F. J. Kurdahi , A. C. Parker, REAL: a program for REgister ALlocation, Proceedings of the 24th ACM/IEEE conference on Design automation, p.210-215, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37920]
	15	Raul Camposano , Reinaldo A. Bergamaschi, Redesign using state splitting, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	16	"Benchmarks for the 5th International Workshop on High-Level Synthesis," 1991. Available through EMail at HLSW@decwrI.dec.com (InterNet).
	17	John A. Darringer , Daniel Brand , John V. Gerbi , William H. Joyner, Jr. , Louise Trevillyan, LSS: a system for production logic synthesis, IBM Journal of Research and Development, v.28 n.5, p.537-545, September 1984