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RICE: Rapid interconnect circuit evaluator

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 555 - 560

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Curtis L. Ratzlaff	The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, TX
Nanda Gopal	The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, TX
Lawrence T. Pillage	The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, TX

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 16, Downloads (12 Months): 33, Citation Count: 49

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Rathin Putatunda, Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips, Proceedings of the 19th conference on Design automation, p.616-621, January 1982
	2	L. Pillage and R. Rohrer. Asymptotic Waveform Evaluation for Timing Analysis. IEEE Transactions on Computer-Aided Design, April 1990.
	3	X. Huang, V. Raghavan and R. A. Rohrer. AWEsim: A Program for the Efficient Analysis of Linear(ized) Circuits. International Conference on Computer-Aided Design, November 1990.
	4	PSPICE Users Manual. MicroSim Corporation. Version 4.03, January, 1990.
	5	Y. Shamash, Stable Reduced-Order Models Using Pade'-Type Approximations. IEEE Trans. Automatic Control, AC- 19:615-616, 1974.
	6	W.C. Elmore. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, Journal of Applied Physics, 19(1):55-63, 1948.
	7	C.L Terman. Simulation Tools for Digital LSI Design. Phl) thesis, Massachusetts institute of Technology, September 1983.
	8	L Rubenstein, P. Penfield, Jr. and M.A. Horowitz. Signal Delay in RC Tree Networks. IEEE Trans. on Computer Aided Design, CAD-2:202-211, 1983.
	9	C. Chu and M. Horowitz. Charge-Sharing Models for Switch- Level Simulation. IEEE Trans. on Computer-Aided Design, 6(6):1053-1060, 1987.
	10	P.R. O'Brien and T.L. Savarino. Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation. International Conference on Computer-Aided Design, November 1989.
	11	L.T. Pillage and S. Dutta. A Path Tracing Algorithm for Asymptotic Waveform Evaluation of Lumped RLC Circuit Delay Models. ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, August 1990.
	12	L.T. Pillage, Xiaoli Huang and R.A. Rohrer. Asymptotic Waveform Evaluation for Circuits Containing Floating Nodes. IEEE International Symposium on Circuits and Systems, May 1990.
	13	C.L. Ratzlaff. A Fast Algorithm for Computing the Time Moments of RLC Circuits. Master's thesis, University of Texas at Austin, May 1991.
	14	G. Kron. Tensor Analysis of Networks. Wiley, New York, N.Y., 1939.
	15	D. Stark and M. Horowitz. Techniques for Calculating the Currrents and Voltages in VLSI Power Supply Networks. IEEE Trans. on Computer-Aided Design, 9(2): 126-132, 1990.
	16	Sergio Pissanetksy, Sparse Matrix Technology, Academic Press, London, 1984.
	17	L. Nagel and R. Rohrer. Computer Analysis of Nonlinear Circuits, Excluding Radiation (CANCER). IEEE J. of Solid State Circuits, August 1971.
	18	Xiaoli Huang. Pade' Approximation of Linear(ized) Circuit Responses. PhD thesis, Carnegie Mellon University, November 1990.
	19	N. Gopal and L. Pillage. Constrained Approximation of Dominant Time Constants in RC Circuit Delay Models. UT- CERC-TR-LTP91-01, November 1990.
	20	N. Gopal, C. Ra~laff and L. Pillage. Constrained Approximation of Dominant Time Constants in RC Circuit Delay Models. Pro~. of the International Mathematics and Computation Symposium, (Invited Paper) July 1991.

CITED BY 49

	Haifang Liao , Wayne Wei-Ming Dai , Rui Wang , Fung-Yuel Chang, S-parameter based macro model of distributed-lumped networks using exponentially decayed polynomial function, Proceedings of the 30th international conference on Design automation, p.726-731, June 14-18, 1993, Dallas, Texas, United States
	Noel Menezes , Satyamurthy Pullela , Lawrence T. Pileggi, Simultaneous gate and interconnect sizing for circuit-level delay optimization, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.690-695, June 12-16, 1995, San Francisco, California, United States
	E. Chiprout , M. Nakhla, Generalized moment-matching methods for transient analysis of interconnect networks, Proceedings of the 29th ACM/IEEE conference on Design automation, p.201-206, June 08-12, 1992, Anaheim, California, United States
	Sudip K. Nag , Rob A. Rutenbar, Performance-driven simultaneous place and route for row-based FPGAs, Proceedings of the 31st annual conference on Design automation, p.301-307, June 06-10, 1994, San Diego, California, United States
	N. H. Chang , K.-J. Chang , J. Leo , K. Lee , S.-Y. Oh, IPDA: interconnect performance design assistant, Proceedings of the 29th ACM/IEEE conference on Design automation, p.472-477, June 08-12, 1992, Anaheim, California, United States
	D. F. Anastasakis , N. Gopal , S. Y. Kim , L. T. Pillage, On the stability of moment-matching approximations in asymptotic waveform evaluation, Proceedings of the 29th ACM/IEEE conference on Design automation, p.207-212, June 08-12, 1992, Anaheim, California, United States
	Lawrence Pileggi, Coping with RC(L) interconnect design headaches, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.246-253, November 05-09, 1995, San Jose, California, United States
	Shantanu Ganguly , Daksh Lehther , Satyamurthy Pullela, Clock Distribution Methodology for PowerPC™Microprocessors, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.181-189, June/July 1997
	Florentin Dartu , Noel Menezes , Jessica Qian , Lawrence T. Pillage, A gate-delay model for high-speed CMOS circuits, Proceedings of the 31st annual conference on Design automation, p.576-580, June 06-10, 1994, San Diego, California, United States
	Jiang Hu , Sachin S. Sapatnekar, Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model, Proceedings of the 1999 international symposium on Physical design, p.133-138, April 12-14, 1999, Monterey, California, United States
	Keith Nabors , Tze-Ting Fang , Hung-Wen Chang , Kenneth S. Kundert, Lumped interconnect models via Gaussian quadrature, Proceedings of the 34th annual conference on Design automation, p.40-45, June 09-13, 1997, Anaheim, California, United States
	Lawrence Pileggi, Timing metrics for physical design of deep submicron technologies, Proceedings of the 1998 international symposium on Physical design, p.28-33, April 06-08, 1998, Monterey, California, United States
	M. Sriram , S. M. Kang, Fast approximation of the transient response of Lossy Transmision Line Trees, Proceedings of the 30th international conference on Design automation, p.691-696, June 14-18, 1993, Dallas, Texas, United States
	Vasant B. Rao, Delay analysis of the distributed RC line, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.370-375, June 12-16, 1995, San Francisco, California, United States
	Noel Menezes , Satyamurthy Pullela , Florentin Dartu , Lawrence T. Pillage, RC interconnect synthesis—a moment fitting approach, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.418-425, November 06-10, 1994, San Jose, California, United States
	Seok-Yoon Kim , Nanda Gopal , Lawrence T. Pillage, AWE macromodels of VLSI interconnect for circuit simulation, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.64-70, November 1992, Santa Clara, California, United States
	Yehea I. Ismail , Eby G. Friedman , Jose L. Neves, Equivalent Elmore delay for RLC trees, Proceedings of the 36th ACM/IEEE conference on Design automation, p.715-720, June 21-25, 1999, New Orleans, Louisiana, United States
	S. Y. Kim , E. Tuncer , R. Gupta , B. Krauter , T. Savarino , D. P. Neikirk , L. T. Pillage, An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.58-65, November 07-11, 1993, Santa Clara, California, United States
	Jiang Hu , Sachin S. Sapatnekar, FAR-DS: full-plane AWE routing with driver sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.84-89, June 21-25, 1999, New Orleans, Louisiana, United States
	Andrew B. Kahng , Kei Masuko , Sudhakar Muddu, Analytical delay models for VLSI interconnects under ramp input, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.30-36, November 10-14, 1996, San Jose, California, United States
	Yehea I. Ismail, Efficient model order reduction via multi-node moment matching, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.767-774, November 10-14, 2002, San Jose, California
	Satyamurthy Pullela , Noel Menezes , Lawrence T. Pillage, Reliable non-zero skew clock trees using wire width optimization, Proceedings of the 30th international conference on Design automation, p.165-170, June 14-18, 1993, Dallas, Texas, United States
	U. Fassnacht , J. Schietke, Timing analysis and optimization of a high-performance CMOS processor chipset, Proceedings of the conference on Design, automation and test in Europe, p.325-330, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Xiaodong Yang , Walter H. Ku , Chung-Kuan Cheng, RLC interconnect delay estimation via moments of amplitude and phase response, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.208-213, November 07-11, 1999, San Jose, California, United States
	Kanak Agarwal , Dennis Sylvester , David Blaauw, Simple metrics for slew rate of RC circuits based on two circuit moments, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	R. W. Freund , P. Feldmann, Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.280-287, November 10-14, 1996, San Jose, California, United States
	Shantanu Ganguly , Shervin Hojat, Clock distribution design and verification for PowerPC microprocessors, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.58-61, November 05-09, 1995, San Jose, California, United States
	Haihua Su , Kaushik Gala , Sachin S. Sapatnekar, Fast analysis and optimization of power/ground networks, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Noel Menezes , Ross Baldick , Lawrence T. Pileggi, A sequential quadratic programming approach to concurrent gate and wire sizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.144-151, November 05-09, 1995, San Jose, California, United States
	V. Raghavan , J. E. Bracken , R. A. Rohrer, AWESpice: a general tool for the accurate and efficient simulation of interconnect problems, Proceedings of the 29th ACM/IEEE conference on Design automation, p.87-92, June 08-12, 1992, Anaheim, California, United States
	Yehea I. Ismail, Improved model-order reduction by using spacial information in moments, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.900-908, October 2003
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