Incremental techniques for the identification of statically sensitizable critical paths

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Incremental techniques for the identification of statically sensitizable critical paths

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 541 - 546

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Yun-Cheng Ju	Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
Resve A. Saleh	Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 31, Citation Count: 10

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	BRA90	Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123222]
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	MCG89	P. C. McGeer , R. K. Brayton, Efficient algorithms for computing the longest viable path in a combinational network, Proceedings of the 26th ACM/IEEE conference on Design automation, p.561-567, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74476]
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	PER89	S. Perremans , L. Claesen , H. De Man, Static timing analysis of dynamically sensitizable paths, Proceedings of the 26th ACM/IEEE conference on Design automation, p.568-573, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74477]
	OUS85	J. Ousterhout, "A Switch-Level Timing Verifier for Digital MOS VLSI", IEEE Transactions on Computer-Aided Design, CAD-4 (no.3), pp. 336-349, July 1985.
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CITED BY 10

	Ronn B. Brashear , Douglas R. Holberg , M. Ray Mercer , Lawrence T. Pillage, ETA: electrical-level timing analysis, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.258-262, November 1992, Santa Clara, California, United States
	Pankaj Pant , Vivek De , Abhijit Chatterjee, Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks, Proceedings of the 34th annual conference on Design automation, p.403-408, June 09-13, 1997, Anaheim, California, United States
	Hoon Chang , Jacob A. Abraham, VIPER: an efficient vigorously sensitizable path extractor, Proceedings of the 30th international conference on Design automation, p.112-117, June 14-18, 1993, Dallas, Texas, United States
	Andrew B. Kahng , Xu Xu, Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Cristinel Ababei , Hushrav Mogal , Kia Bazargan, Three-dimensional place and route for FPGAs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	C. N. Sze , Charles J. Alpert , Jiang Hu , Weiping Shi, Path based buffer insertion, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Cristinel Ababei , Navaratnasothie Selvakkumaran , Kia Bazargan , George Karypis, Multi-objective circuit partitioning for cutsize and path-based delay minimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.181-185, November 10-14, 2002, San Jose, California
	Tao Luo , David Newmark , David Z. Pan, A new LP based incremental timing driven placement for high performance designs, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Hoon Chang , Jacob A. Abraham, An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems, Journal of Electronic Testing: Theory and Applications, v.11 n.2, p.119-129, Oct. 1997
	Hakan Yalcin , John P. Hayes, Event propagation conditions in circuit delay computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.3, p.249-280, July 1997