The effects of physical design characteristics on the area-performance tradeoff curve

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The effects of physical design characteristics on the area-performance tradeoff curve

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 530 - 534

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Alice C. Parker	Department of Electrical Engineering, University of Southern California, Los Angeles, CA
Pravil Gupta	Department of Electrical Engineering, University of Southern California, Los Angeles, CA
Agha Hussain	Department of Electrical Engineering, University of Southern California, Los Angeles, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 15, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Barbacci and D. Siewiorek. The CMU RT- CAD System: An Innovative Approach to Computer Aided Design. In American Federation of Information Processing Societies Conference Proceedings, Vol. ~5, pages 643-655. Amer. Fed. of Information Processing Societies, June 1976.
	2	L. Hafer and A. Parker. Automated Synthesis of Digital Hardware. IEEE Transactions on Computers, C-31(2):93-109, February 1981.
	3	John J. Granacki , Alice C. Parker, The effect of register-transfer design tradeoffs on chip area and performance, Proceedings of the 20th conference on Design automation, p.419-424, June 27-29, 1983, Miami Beach, Florida, United States
	4	E. Girczyc. Automatic Generation of Microsequenced Data Paths to Realize ADA Circuit Descriptions. PhD thesis, Carleton University, 1984.
	5	Michael C. McFarland, Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.474-480, July 1986, Las Vegas, Nevada, United States
	6	Michael McFarland. Reevaluating the Design Space for Register-Transfer Hardware Synthesis. In International Conference on Computer-Aided Design, pages 262-265. IEEE, November 1987.
	7	David W. Knapp, Datapath optimization using feedback, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	8	F. Brewer and D. Gajski. Chippe" A System for Constraint Driven Behavioral Synthesis. IEEE Trans. on Compuler-Aided Design, 9(7)'681-695, July 1990.
	9	R. Jain , K. Kücükcakar , M. J. Mlinar , A. C. Parker, Experience with ADAM synthesis system, Proceedings of the 26th ACM/IEEE conference on Design automation, p.56-61, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74393]

CITED BY 4

	Subhrajit Bhattacharya , Sujit Dey , Franc Brglez, Clock period optimization during resource sharing and assignment, Proceedings of the 31st annual conference on Design automation, p.195-200, June 06-10, 1994, San Diego, California, United States
	Peng-Cheng Kao , Chih-Kuang Hsieh , Allen C.-H. Wu, An RTL design-space exploration method for high-level applications, Proceedings of the 2001 conference on Asia South Pacific design automation, p.162-168, January 2001, Yokohama, Japan
	Pravil Gupta , Alice C. Parker, SMASH: a program for scheduling memory-intensive application-specific hardware, Proceedings of the 7th international symposium on High-level synthesis, p.54-59, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
	Jen-Pin Weng , Alice C. Parker, 3D scheduling: high-level synthesis with floorplanning, Proceedings of the 28th conference on ACM/IEEE design automation, p.668-673, June 17-22, 1991, San Francisco, California, United States