| Industrial extensions to university high level synthesis tools: Making it work in the real world |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 28th ACM/IEEE Design Automation Conference
table of contents
San Francisco, California, United States
Pages: 520 - 525
Year of Publication: 1991
ISBN:0-89791-395-7
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Downloads (6 Weeks): 7, Downloads (12 Months): 10, Citation Count: 4
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Robin C. Sarma , Mark D. Dooley , N. Craig Newman , Graham Hetherington, High-level synthesis: technology transfer to industry, Proceedings of the 27th ACM/IEEE conference on Design automation, p.549-554, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123399]
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Donald E. Thomas , Elizabeth D. Lagnese , John A. Nestor , Jayanth V. Rajan , Robert L. Blackburn , Robert A. Walker, Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, Norwell, MA, 1989
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Mario R. Barbacci, Instruction Set Processor Specifications(ISPS): The Notation and Its Applications, IEEE Trans. Computers, vol. C-30, no. 1, January, 1981, pp. 24-40.
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Robert A. Walker, Design Representation and Behavioral Transformation for Algorithmic Level Integrated Circuit Design, Department of Electrical and Computer Engineering, Carnegie Mellon University, CMUCAD-88-20, April, 1988.
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John A. Nestor, Specification and Synthesis of Digital Systems with Interfaces, Department of Electrical and Computer Engineering, Carnegie Mellon University, CMUCAD-87- 10, April, 1987.
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Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, and Robert A. Walker, Automatic Data Path Synthesis, IEEE Computer, December, 1983, pp. 59-90.
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Lawrence F. Amstein, Describing Systems for High Level Synthesis in the Verilog Language, Department of Electrical and Computer Engineering, Carnegie Mellon University, CMUCAD--90-51, December, 1990.
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T. Fuhrman, D. Thomas, R. Murgai, E. Un, Verification of High Level Synthesis Design Through Gate Level Simulation of Compiled Module Implementations, Proc. 1990 International Symposium on Circuits and Systems, May, 1990.
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CITED BY 5
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E. Berrebi , P. Kission , S. Vernalde , S. De Troch , J. C. Herluison , J. Fréhel , A. A. Jerraya , I. Bolsens, Combined control flow dominated and data flow dominated high-level synthesis, Proceedings of the 33rd annual conference on Design automation, p.573-578, June 03-07, 1996, Las Vegas, Nevada, United States
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Imed Moussa , Zoltan Sugar , Rodolph Suescun , Mario Diaz-Nava , Marco Pavesi , Salvatore Crudo , Luca Gazi , Ahmed Amine Jerraya, Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper, Proceedings of the 36th ACM/IEEE conference on Design automation, p.598-603, June 21-25, 1999, New Orleans, Louisiana, United States
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R. A. Bergamaschi , R. A. O'Connor , L. Stok , M. Z. Moricz , S. Prakash , A. Kuehlmann , D. S. Rao, High-level synthesis in an industrial environment, IBM Journal of Research and Development, v.39 n.1-2, p.131-148, Jan./March 1995
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