Exact width and height minimization of CMOS cells

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Exact width and height minimization of CMOS cells

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 487 - 493

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Robert L. Maziasz	Advanced Computer Architecture Laboratory, Dept. of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
John P. Hayes	Advanced Computer Architecture Laboratory, Dept. of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 9, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	BA88	Donald G. Baltus , Jonathan Allen, SOLO: a generator of efficient layouts from optimized MOS circuit schematics, Proceedings of the 25th ACM/IEEE conference on Design automation, p.445-452, June 12-15, 1988, Atlantic City, New Jersey, United States
	Ba89	R. Bar-Yehuda et al., "Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation," IEEE Trans. Computer-Aided Design, vol. CAD-8, pp. 737-743, July 1989.
	CH88	C. Y. R. Chen and C. Y. Hou, "A new layout optimization methodology for CMOS complex gates," Proc. lnternat. Conf. on C~mputer'Aided Design, pp. 368-371, Nov.1988.
	Hi85	D. Hill, "Se2: A hybrid automatic layout system," Proc. lnternat. Conf. on CAD, pp. 172-174, Nov. 1985.
	HH90	Yung-Ching Hsieh , Chi-Yi Hwang , Youn-Long Lin , Yu-Chin Hsu, LiB: a cell layout generator, Proceedings of the 27th ACM/IEEE conference on Design automation, p.474-479, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123343]
	HS88	Y.M. Huang and M. Sarrafzadeh, "Parallel algorithms for minimum dual-cover with application to CMOS layout," Proc. Internat. Conf. on Parallel Processing, pp. 26-33, Aug. 1988.
	KW85	P. W. Kollaritsch and N. H. E. Weste, "TOPOLOGIZER: An expert system translator of transistor connectivity to symbolic cell layout," IEEE Journal of Solid-State Circuits, vol. SC-20, no. 3, pp. 799-804, June 1985.
	KK88	Y. Kwon and C. Kyung, "A fast heuristic for optimal CMOS functional cell layout generation," Proc. IEEE Int. Syrup. Circuits and Syst., pp.2423-2426, 1988.
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	Ma89	J. Madsen, "A new approach to optimal cell synthesis," Proc. Int. Conf. Computer-Aided Design, pp. 336-339, 1989.
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	Ma85	T. Mano et al., "OCCAM to CMOS," in Computer Hardware Description Languages and their Applications, (C.J. Koomen and T. Moto-oka, eds.) North-Holland: pp. 381-390, 1985.
	Ma91	Robert L. Maziasz, Exact layout area minimization of static CMOS cells, University of Michigan, Ann Arbor, MI, 1991
	MH87	R. L. Maiasz , J. P. Hayes, Layout optimization of CMOS functional cells, Proceedings of the 24th ACM/IEEE conference on Design automation, p.544-551, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37969]
	MH90	R.L. Maziasz and J. P. Hayes, "Layout optimization of static CMOS functional cells," IEEE Trans. Computer:Aided Design, vol. CAD-9, pp. 708-719, July 1990.
	NB85	R. Nair, A. Bruss and J. Reif, "Linear time algorithms for optimal CMOS layout," VLSh Algorithms and Architectures, Elsevier, North Holland, pp. 327-338, 1985.
	OL89	C.-L. Ong , J.-T. Li , C.-Y. Lo, GENAC: an automatic cell synthesis tool, Proceedings of the 26th ACM/IEEE conference on Design automation, p.239-244, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74423]
	Uv81	T. Uehara and W. M. vanCleemput, "Optimal layout of CMOS functional arrays," IEEE Trans. Comput., vol. C-30, pp. 305-312, May 1981.
	Wi87	S. Wimer et al., "Optimal chaining of CMOS transistors in a functional cell," IEEE Trans. on Computer-Aided Design, vol. CAD-6, pp. 795-801, Sept. 1987.

CITED BY 3

	Tetsuya Iizuka , Makoto Ikeda , Kunihiro Asada, High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.149-154, January 27-30, 2004, Yokohama, Japan
	Tetsuya Iizuka , Makoto Ikeda , Kunihiro Asada, Exact minimum-width transistor placement without dual constraint for CMOS cells, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Avaneendra Gupta , Siang-Chun The , John P. Hayes, XPRESS: A Cell Layout Generator with Integrated Transistor Folding, Proceedings of the 1996 European conference on Design and Test, p.393, March 11-14, 1996