A probabilistic testability measure for delay faults

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A probabilistic testability measure for delay faults

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 440 - 445

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Wen Ching Wu	National Chiao Tung Univ., Hsin-Chu, Taiwan, R.O.C.
Chung Len Lee	National Chiao Tung Univ., Hsin-Chu, Taiwan, R.O.C.

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 11, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	G.L. Smith, "Model for Delay Faults Based Upon Paths," Proc. 1985 Int. Test Conf., Nov. 1985, pp.342,-349.
	2	T. Hayashi et al., "A Delay Test Generator for Logic LSI," Proc. 1983 int. Test Conf., Oct. 1983, pp.560--571.
	3	J. Savir , W. H. McAnney, Random Pattern Testability of Delay Faults, IEEE Transactions on Computers, v.37 n.3, p.291-300, March 1988 [doi>10.1109/12.2166]
	4	C.J. Lin and S.M. Reddy, "On Delay Fault Testing in Logic Circuits," IEEE Trans. on CAD, Sept. 1987, pp.694--703.
	5	A.K. Pramanick and G.M. Reddy, "On the Detection of Delay Faults," Proc. 1988 Int. Test Conf., Sept. 1988, pp.g45-g56.
	6	E.S. Park and M.R. Mercer, "Robust and Nonrobust Tests for Path Delay Faults in a Combinational Circuit," Proc. 1987 Int. Test Conf., Sept. 1987, pp.1027--1034.
	7	L.H. Goidstein, "Controllability /Observability Analysis of Digital Circuits," IEEE Trans. on Circuits and Systems, Sept. 1979, pp.685~693.
	8	F. Brglez et al., "Applications of Testability Analysis : From ATPG to Critical Delay Path Tracing," Proc. 1984 Int. Test Conf., 1984, pp.705--712.
	9	Hans-Joachim Wunderlich, PROTEST: a tool for probabilistic testability analysis, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.204-211, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317858]
	10	C.L. Lee, W.Z. Shen, M.S. Wang and J.E. Chert, "Random Test Pattern Generation Aided with a Probabilistic Testability Measure Program," 2nd Workshop on CAD for VLSI, Taiwan, R.O.C., 1990.
	11	F. Brglez et al. "Recent Algorithms for Gate-level ATPG with Fault Simulation and Their Performance Assessment," Int. Symp. Circuits and Systems, IEEE, pp.663~698, June, 1985.
	12	F. Brglez et al. "Combinational Profiles of Sequential Benchmark Circuits," Int. Symp. Circuits and Systems, IEEE, pp.1929~1953, 1989.
	13	Breuer and Friendman, "Diagonosis and Reliable Design of Digital System".