Branch-and-bound placement for building block layout

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Branch-and-bound placement for building block layout

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 433 - 439

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Hidetoshi Onodera	Department of Electrical Engineering and Computer Siences, University of California, Berkeley, CA and Department of Electronics, Kyoto University, Sakyo-ku, Kyoto 606 Japan
Yo Taniguchi	Department of Electronics, Kyoto University, Sakyo-ku, Kyoto 606 Japan
Keikichi Tamaru	Department of Electronics, Kyoto University, Sakyo-ku, Kyoto 606 Japan

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 33, Citation Count: 23

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	B. Preas and M. Lorenzetti, ed., Physical Design Automation of VLSI Systems, The Benjamin/Cummings Publishing Company, California, 1988.
	2	Ralph H.J.M. Otten, Automatic floorplan design, Proceedings of the 19th conference on Design automation, p.261-267, January 1982
	3	Ulrich Lauther, A min-cut placement algorithm for general cell assemblies based on a graph representation, Proceedings of the 16th Conference on Design automation, p.1-10, June 25-27, 1979, San Diego, CA, United States
	4	G. J. Wipfler , M. Wiesel , D. A. Mlynski, A combined force and cut algorithm for hierarchical VLSI layout, Proceedings of the 19th conference on Design automation, p.671-677, January 1982
	5	H. Onodera, M. Sakamoto, T. Kurihara, and K. Tamam, "Step by Step Placement Strategies for Building Block Layout," Proc. 1989 Int. Syrup. on Circuits and Systems, pp. 921-926, 1989.
	6	D. Jepsen and'C. Gelatt, "Macro Placement by Monte Carlo Annealing," in Proc. 1983 IEEE Int. Conf. in Comp. Design, pp. 495-498, Nov. 1983.
	7	Carl Sechen, Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing, Proceedings of the 25th ACM/IEEE conference on Design automation, p.73-80, June 12-15, 1988, Atlantic City, New Jersey, United States
	8	D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States
	9	B. T. Preas , W. M. vanCleemput, Placement algorithms for arbitrarily shaped blocks, Proceedings of the 16th Conference on Design automation, p.474-480, June 25-27, 1979, San Diego, CA, United States
	10	W. M. Dai and E. S. Kuh, "Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout," IEEE Trans. Computer-AidedDesign, vol. CAD-6, pp. 828-837, ScpL 1987.
	11	H. Onodera, Y. Taniguchi, and K. Tamam, "Branch-and-Bound Placement for Building Block Layout," International Workshop on Layout Synthesis, May. 1990.
	12	R. Nail C. L. Berman, P. S. Hauge, and E. J. Yoffa,"Generation of Performance Constraints for Layout," IEEE Trans. Computer-Aided Design, vol. 8, pp. 860--874, Aug. 1989.
	13	M. Schlag, Y. Z. Liao, and C. K. Wong, "An Algorithm for Optimal Two-Dimensional Compaction of VLSI Layouts," Integration, vol. 1, pp. 179-209, Sept. 1983.
	14	G. Kedem and H. Watanabe, "Graph-Optimization Techniques for IC Layout and Compaction," IEEE Trans. Computer-Aided Design, vol. CAD-3, pp. 12-20, Jan. 1984.
	15	W.M. Dai, B. Eschermann, E. S. Kuh, and M. Pedram, "Hierarchical Placement and Floorplanning in BEAR," IEEE Trans. Computer-Aided Design, vol. 8, pp. 1335-1349, Dec. 1989.
	16	Michael Upton , Khosrow Samii , Stephen Sugiyama, Integrated placement for mixed macro cell and standard cell designs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.32-35, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123219]

CITED BY 23

	Shigetoshi Nakatake , Keishi Sakanushi , Yoji Kajitani , Masahiro Kawakita, The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.418-425, November 08-12, 1998, San Jose, California, United States
	Pei-Ning Guo , Chung-Kuan Cheng , Takeshi Yoshimura, An O-tree representation of non-slicing floorplan and its applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.268-273, June 21-25, 1999, New Orleans, Louisiana, United States
	Andrew B. Kahng, Classical floorplanning harmful?, Proceedings of the 2000 international symposium on Physical design, p.207-213, May 2000, San Diego, California, United States
	Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States
	Sheqin Dong , Xianlong Hong , Youliang Wu , Yizhou Lin , Jun Gu, VLSI block placement using less flexibility first principles, Proceedings of the 2001 conference on Asia South Pacific design automation, p.601-604, January 2001, Yokohama, Japan
	Le-Chin Eugene Liu , Hsiao-Ping Tseng , Carl Sechen, Chip-level area routing, Proceedings of the 1998 international symposium on Physical design, p.197-204, April 06-08, 1998, Monterey, California, United States
	Jin Xu , Pei-Ning Guo , Chung-Kuan Cheng, Cluster refinement for block placement, Proceedings of the 34th annual conference on Design automation, p.762-765, June 09-13, 1997, Anaheim, California, United States
	Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
	Jai-Ming Lin , Yao-Wen Chang, TCG: a transitive closure graph-based representation for non-slicing floorplans, Proceedings of the 38th conference on Design automation, p.764-769, June 2001, Las Vegas, Nevada, United States
	Florin Balasa , Koen Lampaert, Module placement for analog layout using the sequence-pair representation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.274-279, June 21-25, 1999, New Orleans, Louisiana, United States
	Takayuki Yamanouchi , Kazuo Tamakashi , Takashi Kambe, Hybrid floorplanning based on partial clustering and module restructuring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.478-483, November 10-14, 1996, San Jose, California, United States
	Serkan Askar , Maciej Ciesielski, Analytical approach to custom datapath design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.98-101, November 07-11, 1999, San Jose, California, United States
	Henrik Esbensen, A genetic algorithm for macro cell placement, Proceedings of the conference on European design automation, p.52-57, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Jin Xu , Pei-ning Guo , Chung-Kuan Cheng, Rectilinear block placement using sequence-pair, Proceedings of the 1998 international symposium on Physical design, p.173-178, April 06-08, 1998, Monterey, California, United States
	Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States
	Jens Vygen, Algorithms for large-scale flat placement, Proceedings of the 34th annual conference on Design automation, p.746-751, June 09-13, 1997, Anaheim, California, United States
	Florin Balasa, Modeling non-slicing floorplans with binary trees, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Xianlong Hong , Gang Huang , Yici Cai , Jiangchun Gu , Sheqin Dong , Chung Kuan Cheng , Jun Gu, Corner block list: an effective and efficient topological representation of non-slicing floorplan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	SheQin Dong , XianLong Hong , YuLiang Wu , Jun Gu, Deterministic VLSI block placement algorithm using less flexibility first principle, Journal of Computer Science and Technology, v.18 n.6, p.739-746, November 2003
	Hayward H. Chan , Igor L. Markov, Practical slicing and non-slicing block-packing without simulated annealing, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Michael D. Moffitt , Aaron N. Ng , Igor L. Markov , Martha E. Pollack, Constraint-driven floorplan repair, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	David Pisinger , Mikkel Sigurd, Using Decomposition Techniques and Constraint Programming for Solving the Two-Dimensional Bin-Packing Problem, INFORMS Journal on Computing, v.19 n.1, p.36-51, January 2007
	A. J. Pfeiffer , T. Mukherjee , S. Hauan, Simultaneous design and placement of multiplexed chemical processing systems on microchips, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.229-236, November 07-11, 2004