A data path synthesis method for self-testable designs

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A data path synthesis method for self-testable designs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 378 - 384

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Christos A. Papachristou	Department of Computer Engineering, Case Western Reserve University, Cleveland, Ohio
Scott Chiu	Department of Computer Engineering, Case Western Reserve University, Cleveland, Ohio
Haidar Harmanani	Department of Computer Engineering, Case Western Reserve University, Cleveland, Ohio

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 15, Citation Count: 28

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 28

	Haidar Harmanani , Christos A. Papachristou, An improved method for RTL synthesis with testability tradeoffs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.30-35, November 07-11, 1993, Santa Clara, California, United States
	Tien-Chien Lee , Niraj K. Jha , Wayne H. Wolf, Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments, Proceedings of the 30th international conference on Design automation, p.292-297, June 14-18, 1993, Dallas, Texas, United States
	R. Leveugle, Optimized state assignment of single fault tolerant FSMs based on SEC codes, Proceedings of the 30th international conference on Design automation, p.14-18, June 14-18, 1993, Dallas, Texas, United States
	T. Yang , Z. Peng, An efficient algorithm to integrated scheduling and allocation in high-level test synthesis, Proceedings of the conference on Design, automation and test in Europe, p.74-81, February 23-26, 1998, Le Palais des Congrés de Paris, France
	I. Parulkar , S. K. Gupta , M. A. Breuer, Scheduling and module assignment for reducing BIST resources, Proceedings of the conference on Design, automation and test in Europe, p.66-73, February 23-26, 1998, Le Palais des Congrés de Paris, France
	M. Nourani , C. Papachristou, Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems, Proceedings of the 29th ACM/IEEE conference on Design automation, p.99-105, June 08-12, 1992, Anaheim, California, United States
	H. Harmanani , C. Papachristou , S. Chiu , M. Nourani, SYNTEST: an environment for system-level design for test, Proceedings of the conference on European design automation, p.402-407, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Ramesh Karri , Alex Orailoğlu, High-level synthesis of fault-secure microarchitectures, Proceedings of the 30th international conference on Design automation, p.429-433, June 14-18, 1993, Dallas, Texas, United States
	Han Bin Kim , Dong Sam Ha , Takeshi Takahashi, On ILP formulations for built-in self-testable data path synthesis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.742-747, June 21-25, 1999, New Orleans, Louisiana, United States
	Tien-Chien Lee , Wayne H. Wolf , Niraj K. Jha, Behavioral synthesis for easy testability in data path scheduling, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.616-619, November 1992, Santa Clara, California, United States
	Ishwar Parulkar , Sandeep Gupta , Melvin A. Breuer, Data path allocation for synthesizing RTL design with low BIST area overhead, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.395-401, June 12-16, 1995, San Francisco, California, United States
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Introducing redundant computations in RTL data paths for reducing BIST resources, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.423-445, July 2001
	Ravibala Singh , John Knight, Concurrent testing in high-level synthesis, Proceedings of the 7th international symposium on High-level synthesis, p.96-103, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
	Albrecht P. Stroele , Hans-Joachim Wunderlich, Test register insertion with minimum hardware cost, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.95-101, November 05-09, 1995, San Jose, California, United States
	Kenneth D. Wagner , Sujit Dey, High-level synthesis for testability: a survey and perspective, Proceedings of the 33rd annual conference on Design automation, p.131-136, June 03-07, 1996, Las Vegas, Nevada, United States
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Lower bounds on test resources for scheduled data flow graphs, Proceedings of the 33rd annual conference on Design automation, p.143-148, June 03-07, 1996, Las Vegas, Nevada, United States
	Nektarios Kranitis , Antonis Paschalis , Dimitris Gizopoulos , Mihalis Psarakis , Yervant Zorian, An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths, Journal of Electronic Testing: Theory and Applications, v.17 n.2, p.97-107, April 2001
	Chouki Aktouf , Hérvé Fleury , Chantal Robach, Inserting Scan at the Behavioral Level, IEEE Design & Test, v.17 n.3, p.34-42, July 2000
	Giacomo Buonanno , MariaGiovanna Sami, Co-Testing: Granting Testability in a Codesign Environment, Integrated Computer-Aided Engineering, v.5 n.1, p.7-18, January 1998
	Joan E. Carletta , Christos A. Papachristou, Behavioral Testability Insertion for Datapath/Controller Circuits, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.9-28, Aug. 1997
	Albrecht P. Stroele, BIST Pattern Generators Using Addition and Subtraction Operations, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.69-80, Aug. 1997
	Jian Shen , Jacob A. Abraham, Synthesis of Native Mode Self-Test Programs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.137-148, Oct. 1998
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	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Allocation Techniques for Reducing BIST Area Overhead ofData Paths, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.149-166, Oct. 1998
	Christos A. Papachristou , Mikhail Baklashov , Kowen Lai, High-Level Test Synthesis for Behavioral and Structural Designs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.167-188, Oct. 1998
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Estimation of BIST Resources During High-Level Synthesis, Journal of Electronic Testing: Theory and Applications, v.13 n.3, p.221-237, Dec. 1998
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Estimation of BIST Resources During High-Level Synthesis, Journal of Electronic Testing: Theory and Applications, v.13 n.3, p.221-237, Dec. 1998
	M. L. Flottes , D. Hammad , B. Rouzeyre, High-level synthesis for easy testability, Proceedings of the 1995 European conference on Design and Test, p.198, March 06-09, 1995