A synthesis-based test generation and compaction algorithm for multifaults

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A synthesis-based test generation and compaction algorithm for multifaults

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 359 - 365

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Srinivas Devadas	Department of EECS, MIT, Cambridge, MA
Kurt Keutzer	Synopsys, Mountain View, CA
Sharad Malik	Department of EE, Princeton University, NJ

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 9, Downloads (12 Months): 17, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Pranav Ashar , Srinivas Devadas , Kurt Keutzer, Testability properties of multilevel logic networks derived from binary decision diagrams, Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI, p.35-54, April 1991
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