A transitive closure based algorithm for test generation

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

A transitive closure based algorithm for test generation

Full text

Pdf (660 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 353 - 358

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Srimat T. Chakradhar	NEC Research Institute, Princeton, NJ
Vishwani D. Agrawal	AT&T Bell Laboratories, Murray Hill, NJ

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 13, Citation Count: 3

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/127601.127693 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E Brglez and H. Fujiwara. A Neutral Netlist of 10 Combinatorial Benchmark Circuits and a Target Translator in FORTRAN. In Prec. IEEE Intl. Syrup. on Circ. and Syst., pages 663-698, June 1985.
	2	Srimat Tirumala Chakradhar, Neural network models and optimization methods for digital testing, Rutgers University, New Brunswick, NJ, 1991
	3	Srimat T. Chakradhar , Vishwani D. Agrawal , Michael L. Bushnell, Automatic test generation using quadratic 0-1 programming, Proceedings of the 27th ACM/IEEE conference on Design automation, p.654-659, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123430]
	4	Srimat Chakradhar , Vishwani Agrawal , Michael Bushnell , Thomas Truong, Neural Net and Boolean Satisfiability Models of Logic Circuits, IEEE Design & Test, v.7 n.5, p.54-57, September 1990 [doi>10.1109/54.60606]
	5	T.H. Cormen, C. E. Leiserson, and R. L. Rivest. introduction to Alger~thins. McGraw Hill, New York, 1990.
	6	H. Fujiwara and T. Shimono. On the Acceleration of Test Generation Algorithms. IEEE Trans. on Comput., C-32(12):1137-1144, Dec. 1983.
	7	John Giraldi , Michael L. Bushnell, EST: The new frontier in automatic test-pattern generation, Proceedings of the 27th ACM/IEEE conference on Design automation, p.667-672, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123434]
	8	P Hansen , B Jaumard , M Minoux, A linear expected-time algorithm for deriving all logical conclusions implied by a set of Boolean inequalities, Mathematical Programming: Series A and B, v.34 n.2, p.223-231, March 1986 [doi>10.1007/BF01580586]
	9	T. Kirkland , M. R. Mercer, A topological search algorithm for ATPG, Proceedings of the 24th ACM/IEEE conference on Design automation, p.502-508, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37963]
	10	Shaunak R. Pawagi , P. S. Gopalakrishnan , I. V. Ramakrishnan, Computing dominators in parallel, Information Processing Letters, v.24 n.4, p.217-221, March 1987 [doi>10.1016/0020-0190(87)90136-0]
	11	J. Rajski and H. Cox. A Method to Calculate Necessary Assignments in Algorithmic Test Pattern Generation. In Prec. IEEE Intl. Test Conf., pages 25-34, Sept. 1990.
	12	P.R. Schneider. On the Necessity to Examine D-Chains in Diagnostic Test Generation. IBM J. ofRes. & Dev., 11(1):114,Jan. 1967.
	13	M.H. Schulz and E. Auth. improved Deterministic Test Pattern Generation with Applications to Redundancy Identification. IEEE Trans. on CAD, 8(7):811-816,July 1989.
	14	B. F. Wang , G. H. Chen, Constant Time Algorithms for the Transitive Closure and Some Related Graph Problems on Processor Arrays with Reconfigurable Bus Systems, IEEE Transactions on Parallel and Distributed Systems, v.1 n.4, p.500-507, October 1990 [doi>10.1109/71.80177]

CITED BY 3

	Kabir Gulrajani , Michael S. Hsiao, Multi-node static logic implications for redundancy identification, Proceedings of the conference on Design, automation and test in Europe, p.729-735, March 27-30, 2000, Paris, France
	Seiji Kajihara , Irith Pomeranz , Kozo Kinoshita , Sudhakar M. Reddy, Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits, Proceedings of the 30th international conference on Design automation, p.102-106, June 14-18, 1993, Dallas, Texas, United States
	Lucas Bordeaux , Youssef Hamadi , Lintao Zhang, Propositional Satisfiability and Constraint Programming: A comparative survey, ACM Computing Surveys (CSUR), v.38 n.4, p.12-es, 2006