On achieving a complete fault coverage for sequential machines using the transition fault model

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On achieving a complete fault coverage for sequential machines using the transition fault model

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 341 - 346

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Irith Pomeranz	Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
Sudhakar M. Reddy	Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 10, Citation Count: 7

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hideo Fujiwara, Logic testing and design for testability, Massachusetts Institute of Technology, Cambridge, MA, 1985
	2	M. Abramovici, M.A. Breuer and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
	3	H-K.T. Ma, S. Devadas, A.R. Newton, and A. S- Vincentelli, "Test Generation for Sequential Circuits", IEEE Trans. CAD, Oct. 1988, pp. 1081-1093.
	4	W-T. Cheng, "The Back Algorithm for Sequential Test Generation", ICCD 1988, pp. 66-69.
	5	R.V. Hudly and S.C. Seth, "Testability Analysis of Synchronous Sequential Circuits Based on Structural Data", Intl. Test Conference, 1989, pp. 364-372.
	6	S.M. Thatte and J.A. Abraham, "Test Generation for Microprocessors", IEEE Trans. Computers, June 1980, pp. 429-441.
	7	K-T. Cheng and J.Y. Jou, "Functional Test Generation for Finite State Machines", Intl. Test Conference, 1990, pp. 162-168.
	8	A.T. Dahbura, M.U. Uyar, and C.W. Yau, "An Optimal Test Sequence for the JTAG/IEEE Pl149.1 Test Access Port Controller", Intl. Test Conference, 1989, pp. 55-62.
	9	F.C. Hennie, Finite-State Models for Logical Machines, Wiley, 1968.

CITED BY 7

	Irith Pomeranz , Sudhakar M. Reddy, On generating compact test sequences for synchronous sequential circuits, Proceedings of the conference on European design automation, p.105-110, September 18-22, 1995, Brighton, England
	Dechang Sun , Bapiraju Vinnakota , Wanli Jiang, Fast state verification, Proceedings of the 35th annual conference on Design automation, p.619-624, June 15-19, 1998, San Francisco, California, United States
	Kwang-Ting Cheng, Gate-level test generation for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.405-442, Oct. 1996
	I. Pomeranz , S. M. Reddy, On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation, IEEE Transactions on Computers, v.43 n.9, p.1100-1105, September 1994
	Bapiraju Vinnakota , Jason Andrews, Functional test generation for FSMs by fault extraction, Proceedings of the 31st annual conference on Design automation, p.712-715, June 06-10, 1994, San Diego, California, United States
	Irith Pomeranz , Sudhakar M. Reddy, The Multiple Observation Time Test Strategy, IEEE Transactions on Computers, v.41 n.5, p.627-637, May 1992
	Sezer Gören , F. Joel Ferguson, Test sequence generation for controller verification and test with high coverage, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.4, p.916-938, October 2006