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A general multi-layer area router
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents
San Francisco, California, United States
Pages: 335 - 340  
Year of Publication: 1991
ISBN:0-89791-395-7
Authors
Mohankumar Guruswamy  Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Tx and MCC, 3500 West Balcones Center Drive, Austin, Tx
D. F. Wong  Department of Computer Sciences, The University of Texas at Austin, Austin, Tx
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 11,   Citation Count: 1
Additional Information:

references   cited by   index terms   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
T. Yoshimura and E. S. Kuh, "Efficient Algorithms for Channel Routing," IEEE Trans. on CAD of lCs and Systems, Vol. CAD- 1, No. 1, 1982, pp. 25-35.
 
2
Ronald L. Rivest , Charles M. Fiduccia, A “greedy” channel router, Proceedings of the 19th conference on Design automation, p.418-424, January 1982
3
Rostam Joobbani , Daniel P. Siewiorek, WEAVER: a knowledge-based routing expert, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.266-272, June 1985, Las Vegas, Nevada, United States  [doi>10.1145/317825.317869]
 
4
Luk, W. K. "A Greedy Switch-box Router," INTEGRATION, the VLSI Journal 3, 1985, pp. 129-149.
 
5
H. Shin and A. Sangiovanni-VincenteUi, "A Detailed Router Based on Incremental Routing Modifications: Mighty," IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No. 6, Nov. 1987, pp. 942-955.
 
6
P-S. Tzeng and C. H. Sequin, "Codar: A Congestion-Directed General Area Router," Proc. oflCCAD (1988) pp. 30-33.
 
7
C. Lee, "An Algorithm for Path Connections and its Applications," IRE Trans. on Electronic Computers, (Sept. 1961), pp. 346-365.
 
8
D. F. Wong , H. W. Leong , C. L. Liu, Simulated annealing for VLSI design, Kluwer Academic Publishers, Norwell, MA, 1988

CITED BY
Le-Chin Eugene Liu , Hsiao-Ping Tseng , Carl Sechen, Chip-level area routing, Proceedings of the 1998 international symposium on Physical design, p.197-204, April 06-08, 1998, Monterey, California, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Routing and layout


General Terms:
Algorithms, Design, Experimentation, Measurement, Performance, Theory

Collaborative Colleagues:
Mohankumar Guruswamy: colleagues
D. F. Wong: colleagues

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