A design for testability scheme with applications to data path synthesis

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A design for testability scheme with applications to data path synthesis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 271 - 277

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Scott Chiu	Department of Computer Engineering and Science, Case Western Reserve University, Cleveland, OH
Christos A. Papachristou	Department of Computer Engineering and Science, Case Western Reserve University, Cleveland, OH

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 12, Citation Count: 17

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Abadir, M. S., and M. Breuer. A Knowledge Based System for Designing Testable VLSI Chips. IEEE Design & Test, August 1985, pp. 56 - 68.
	2	Agrawal, V. D. An Information Theoretic Approach to Digital Fault Testing. IEEE Transactions on Computers, August 1981, pp. 582 - 587.
	3	Avra L., and E. McCluskey. Behavioral Synthesis of Testable Systems with VHDL. 1990 IEEE Computer Conference, pp. 410 - 415.
	4	Paul H. Bardell , William H. McAnney , Jacob Savir, Built-in test for VLSI: pseudorandom techniques, Wiley-Interscience, New York, NY, 1987
	5	Frans Beenker , Barry J. Dekker , Richard Stans , Max Van der Star, Implementing Macro Test in Silicon Compiler Design, IEEE Design & Test, v.7 n.2, p.41-51, March 1990 [doi>10.1109/54.53044]
	6	Carlson, S., and P. Wildman. What's Ahead for Testability and Logic Synthesis. IEEE Design & Test, Vol. 7, No. 5, October 1990, pp. 3-4.
	7	F. Catthoor , J. van Sas , L. Inze , H. De Man, A Testability Strategy for Microprocessor Architecture, IEEE Design & Test, v.6 n.2, p.18-34, March 1989 [doi>10.1109/54.19132]
	8	Chen, C. H., and P. R. Menon. An Approach to Functional Level Testability Analysis. 1989 International Test Conference, 1089, pp. 373- 380.
	9	Chiu, S. K., and C. A. Papachristou. A Design for Testability Scheme with Applications to High Level Synthesis. Technical Report CES- 90-35, Department of Computer Engineering & Science, Case Western Reserve University, 1990.
	10	Chiu, S. K., and C. A. Papachristou. A Built- In Self-Testing Scheme for Minimizing Hardware Overhead. Technical Report CES-91-02, Department of Computer Engineering & Science, Case Western Reserve University, 1991.
	11	P. R. Chalasani , S. Bhawmik , A. Acharya , P. Palchaudhuri, Design of Testable VLSI Circuits with Minimum Area Overhead, IEEE Transactions on Computers, v.38 n.10, p.1460-1462, October 1989 [doi>10.1109/12.35841]
	12	Dussault, J. A.. A Testability Measure. 1978 Semiconductor Test Conference, Oct. 1978, pp. 113- 116.
	13	Fung, H. S. and J. Fong. An Information Flow Approach to Functional Testability Measures. 1982 international Conference on Circuits and Systems, pp. 460- 463.
	14	Catherine H. Gebotys , Mohamed I. Elmasry, VLSI design synthesis with testability, Proceedings of the 25th ACM/IEEE conference on Design automation, p.16-21, June 12-15, 1988, Atlantic City, New Jersey, United States
	15	R. Gupta , M. A. Breuer, The Ballast Methodology for Structured Partial Scan Design, IEEE Transactions on Computers, v.39 n.4, p.538-544, April 1990 [doi>10.1109/12.54846]
	16	Hudson, C. L. Jr., and G. D. Peterson. Parallel Self-Test with Pseudo-random Test Patterns. 1987 International Test Conference, September 1987, pp. 954- 963.
	17	Hwang, W. K., M. Lightner, and F. Lombardi. Predicting Fault Coverage for Random Testing of Combinational Circuits. 1987 International Test Conference, September 1987, pp. 843 - 848.
	18	Kiln, K., D. S. Ha, and J. Tront. On Using Signature Registers as Pseudorandom Pattern Generators in Built-in Self-Testing. IEEE Transactions on Computer Aided Design, August 1988, pp. 919 - 928.
	19	LeBlanc, J. J. LOCST: A Built-In Self-Test Technique. IEEE Design & Test, Vol. 1, November 1983, pp. 45 - 52.
	20	Man, H. D., et al. Cathedral II: A Silicon Complier for Digital Signal Processing. IEEE Design & Test, December 1986, pp. 13- 25.
	21	McFarland, M., A. Parker, and R. Compasano. The High Level Synthesis of Digital Systems. Proceedings of the IEEE, Vol. 78, No. 2, February 1990, pp. 301 - 318.
	22	Masud Mansuripur, Introduction to information theory, Prentice-Hall, Inc., Upper Saddle River, NJ, 1987
	23	Papachristou, C. A., S. Chiu, H., Almusa, and H. Harmanani. System Level Design for Testability. Technical Report CES-90-12, Department of Computer Engineering & Science, Case Western Reserve University, 1990.
	24	P. G. Paulin , J. P. Knight, Scheduling and binding algorithms for high-level synthesis, Proceedings of the 26th ACM/IEEE conference on Design automation, p.1-6, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74383]
	25	S. C. Seth , V. D. Agrawal , H. Farhat, A Statistical Theory of Digital Circuit Testability, IEEE Transactions on Computers, v.39 n.4, p.582-586, April 1990 [doi>10.1109/12.54854]
	26	Thearling, K., and J. Abraham. An Easily Computed Functional Level Testability Measure. 1989 International Test Conference, 1989, pp. 381 - 390.

CITED BY 17

	Ian G. Harris , Alex Orailoglu, Microarchitectural synthesis of VLSI designs with high test concurrency, Proceedings of the 31st annual conference on Design automation, p.206-211, June 06-10, 1994, San Diego, California, United States
	Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer, On testable multipliers for fixed-width data path architectures, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.541-547, November 05-09, 1995, San Jose, California, United States
	H. Harmanani , C. Papachristou , S. Chiu , M. Nourani, SYNTEST: an environment for system-level design for test, Proceedings of the conference on European design automation, p.402-407, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Qiushuang Zhang , Ian Harris, Partial BIST insertion to eliminate data correlation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.395-399, November 07-11, 1999, San Jose, California, United States
	Chris Papachristou , Mikhail Baklashov, A test synthesis technique using redundant register transfers, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.414-420, November 09-13, 1997, San Jose, California, United States
	Haidar Harmanani , Christos A. Papachristou, An improved method for RTL synthesis with testability tradeoffs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.30-35, November 07-11, 1993, Santa Clara, California, United States
	Nilanjan Mukherjee , Janusz Rajski , Jerzy Tyszer, Design of Testable Multipliers for Fixed-Width Data Paths, IEEE Transactions on Computers, v.46 n.7, p.795-810, July 1997
	Robert C. Aitken, An Overview of Test Synthesis Tools, IEEE Design & Test, v.12 n.2, p.8-15, June 1995
	M. F. Abdulla , C. P. Ravikumar , Anshul Kumar, Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems, Journal of Electronic Testing: Theory and Applications, v.12 n.3, p.199-216, June 1998
	Joan E. Carletta , Christos A. Papachristou, Behavioral Testability Insertion for Datapath/Controller Circuits, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.9-28, Aug. 1997
	Christos A. Papachristou , Mikhail Baklashov , Kowen Lai, High-Level Test Synthesis for Behavioral and Structural Designs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.167-188, Oct. 1998
	Frank F. Hsu , Janak H. Patel, High-Level Controllability and Observability Analysis for Test Synthesis, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.93-103, Oct. 1998
	Nilanjan Mukherjee , Ramesh Karri, Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.189-200, Oct. 1998
	Kelly A. Ockunzzi , Christos A. Papachristou, Testability Enhancement for Control-Flow Intensive Behaviors, Journal of Electronic Testing: Theory and Applications, v.13 n.3, p.239-257, Dec. 1998
	Nicola Nicolici , Bashir M. Al-Hashimi, Efficient BIST hardware insertion with low test application time for synthesized data paths, Proceedings of the conference on Design, automation and test in Europe, p.60-es, January 1999, Munich, Germany
	M. Nourani , C. Papachristou, Structural BIST Insertion Using Behavioral Test Analysis, Proceedings of the 1997 European conference on Design and Test, p.64, March 17-20, 1997
	J. Carletta , C. Papachristou, A method for testability analysis and BIST insertion at the RTL, Proceedings of the 1995 European conference on Design and Test, p.600, March 06-09, 1995