Benchmarks for layout synthesis—evolution and current status

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Benchmarks for layout synthesis—evolution and current status

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 265 - 270

Year of Publication: 1991

ISBN:0-89791-395-7

Author

Krzysztof Koźmiński

MCNC Center for Microelectronics, P.O. Box 12889, 3021 Cornwallis Road, Research Triangle Park, North Carolina

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 21, Citation Count: 17

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Intl. Wkshp. on Symbolic Layout Compaction, Research Triangle Park, November 1986.
	2	B. Preas, Benchmarks for cell-based layout systems, Proceedings of the 24th ACM/IEEE conference on Design automation, p.319-320, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37936]
	3	D. Boyer, Symbolic Layout Compaction Benchmarks- Introduction and Ground Rules, Proc. Intl. Conf. on Computer Design, 1987, pp 187-191.
	4	Intl. Wkshp. on Placement and Routing, Research Triangle Park, 1988.
	5	Dwight D. Hill , Bryan Preas, Benchmarks for cell synthesis, Proceedings of the 27th ACM/IEEE conference on Design automation, p.317-320, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123287]
	6	R. Camposano, G.DeMicheli, Is there any Hope for "Standard' High-Level Synthesis Benchmarks?, unpublished manuscript.
	7	B. Preas, private communication.
	8	H. Troy Nagle et al., Introduction to Computer Logic, Prentice Hall, 1975, page 461.
	9	F. Brglez, D. Bryan, S. Dey, ASICs as Testability Benchmarks, 14th Annual IEEE Workshop on Design for Testability, Vail, April 16--19, 1991.
	10	F. Brglez, D. Bryan, K. Ko~mifiski, Combinational Profiles of Sequential Benchmark Circuits, Proc. Intl. Symp. on Circuits and Systems, 1989.
	11	For example: Timing-Driven Layout Techniques session at the 1990 Design Automation Conference.

CITED BY 17

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	Elaheh Bozorgzadeh , Ryan Kastner , Majid Sarrafzadeh, Creating and exploiting flexibility in steiner trees, Proceedings of the 38th conference on Design automation, p.195-198, June 2001, Las Vegas, Nevada, United States
	Bernhard M. Riess , Konrad Doll , Frank M. Johannes, Partitioning very large circuits using analytical placement techniques, Proceedings of the 31st annual conference on Design automation, p.646-651, June 06-10, 1994, San Diego, California, United States
	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Can recursive bisection alone produce routable placements?, Proceedings of the 37th conference on Design automation, p.477-482, June 05-09, 2000, Los Angeles, California, United States
	Patrick H. Madden, Reporting of standard cell placement results, Proceedings of the 2001 international symposium on Physical design, p.30-35, April 01-04, 2001, Sonoma, California, United States
	Jason Cong , Patrick H. Madden, Performance driven global routing for standard cell design, Proceedings of the 1997 international symposium on Physical design, p.73-80, April 14-16, 1997, Napa Valley, California, United States
	Tony F. Chan , Jason Cong , Tianming Kong , Joseph R. Shinnerl, Multilevel optimization for large-scale circuit placement, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Wern-Jieh Sun , Carl Sechen, A loosely coupled parallel algorithm for standard cell placement, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.137-144, November 06-10, 1994, San Jose, California, United States
	Ryan Kastner , Elaheh Bozorgzadeh , Majid Sarrafzadeh, An exact algorithm for coupling-free routing, Proceedings of the 2001 international symposium on Physical design, p.10-15, April 01-04, 2001, Sonoma, California, United States
	Ryan Kastner , Elaheh Bozorgzadeh , Majid Sarrafzadeh, Predictable routing, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Yangdong Deng , Wojciech P. Maly, Interconnect characteristics of 2.5-D system integration scheme, Proceedings of the 2001 international symposium on Physical design, p.171-175, April 01-04, 2001, Sonoma, California, United States
	Konrad Doll , Frank M. Johannes , Georg Sigl, Accurate net models for placement improvement by network flow methods, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.594-597, November 1992, Santa Clara, California, United States
	Laleh Behjat , Anthony Vannelli , William Rosehart, Integer Linear Programming Models for Global Routing, INFORMS Journal on Computing, v.18 n.2, p.137-150, Spring 2006
	Laleh Behjat , Anthony Vannelli , William Rosehart, Integer Linear Programming Models for Global Routing, INFORMS Journal on Computing, v.18 n.2, p.137-150, Spring 2006
	Dorothy Kucar , Anthony Vannelli, Using Eigenvectors to Partition Circuits, INFORMS Journal on Computing, v.18 n.2, p.197-208, Spring 2006
	Mehmet Can Yildiz , Patrick H. Madden, Improved cut sequences for partitioning based placement, Proceedings of the 38th conference on Design automation, p.776-779, June 2001, Las Vegas, Nevada, United States
	B. M. Riess , A. A. Schoene, Architecture driven k-way partitioning for multichip modules, Proceedings of the 1995 European conference on Design and Test, p.71, March 06-09, 1995