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Xmap: A technology mapper for table-lookup field-programmable gate arrays

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 240 - 243

Year of Publication: 1991

ISBN:0-89791-395-7

Author

Kevin Karplus

Baskin Center for Computer Engineering & Information Sciences, University of California, Santa Cruz, Santa Cruz, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 11, Citation Count: 36

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. R. C. M. Berkelaar and J. A. G. Jess. Technology mapping for standard-cell generators. In ICCAD-88, pages 470-473, Nov. 1988.
	2	R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang. MIS: a multiple-level logic optimization system. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, CAD-6(6):1062-1081, Nov. 1987.
	3	E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. Technology mapping in MIS. In ICCAD-87, pages 116-119. IEEE Computer Society Press, Nov. 1987.
	4	Robert J. Francis , Jonathan Rose , Kevin Chung, Chortle: a technology mapping program for lookup table-based field programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.613-619, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123418]
	5	David Gregory , Karen Bartlett , Aart de Geus , Gary Hachtel, SOCRATES: a system for automatically synthesizing and optimizing combinational logic, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.79-85, July 1986, Las Vegas, Nevada, United States
	6	Kevin Karplus, Using if-then-else DAGs for multi-level logic minimization, Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI, p.101-117, June 1989, Cambridge, Massachusetts, United States
	7	Kevin Karplus, USING IF-THEN-ELSE DAGS TO DO TECHNOLOGY MAPPING FOR FIELD-PROGRAMMABLE GATE ARRAYS, University of California at Santa Cruz, Santa Cruz, CA, 1990
	8	K. Karplus. Canonical forms of if-then-else dags are robustly path-delay-fault testable. In International Workshop on Logic Synthesis, Research Triangle Park, North Carolina, May 1991. submitted.
	9	K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37940]
	10	R. Mur~;ai. Electronic mail, August 1990.
	11	Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123421]

CITED BY 36

	Chi-Chou Kao , Yen-Tai Lai, An efficient algorithm for finding the minimal-area FPGA technology mapping, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.168-186, January 2005
	Jason Cong , Yuzheng Ding, An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.48-53, November 1992, Santa Clara, California, United States
	Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula, BDD based decomposition of logic functions with application to FPGA synthesis, Proceedings of the 30th international conference on Design automation, p.642-647, June 14-18, 1993, Dallas, Texas, United States
	Jason Cong , Yean-Yow Hwang, Simultaneous depth and area minimization in LUT-based FPGA mapping, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.68-74, February 12-14, 1995, Monterey, California, United States
	Jason Cong , John Peck , Yuzheng Ding, RASP: a general logic synthesis system for SRAM-based FPGAs, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.137-143, February 11-13, 1996, Monterey, California, United States
	Rajeev Murgai , Robert K. Brayton , Albert Sangiovanni-Vincentelli, Sequential synthesis for table look up programmable gate arrays, Proceedings of the 30th international conference on Design automation, p.224-229, June 14-18, 1993, Dallas, Texas, United States
	Yuji Kukimoto , Masahiro Fujita, Rectification method for lookup-table type FPGA's, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.54-61, November 1992, Santa Clara, California, United States
	Michael J. Alexander , James P. Cohoon , Joseph L. Ganley , Gabriel Robins, An architecture-independent approach to FPGA routing based on multi-weighted graphs, Proceedings of the conference on European design automation, p.259-264, September 19-23, 1994, Grenoble, France
	Jason Cong , Yuzheng Ding, On area/depth trade-off in LUT-based FPGA technology mapping, Proceedings of the 30th international conference on Design automation, p.213-218, June 14-18, 1993, Dallas, Texas, United States
	Shashidhar Thakur , D. F. Wong, Series-parallel functions and FPGA logic module design, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.102-122, Jan. 1996
	Zhi-Hong Wang , En-Cheng Liu , Jianbang Lai , Ting-Chi Wang, Power minization in LUT-based FPGA technology mapping, Proceedings of the 2001 conference on Asia South Pacific design automation, p.635-640, January 2001, Yokohama, Japan
	Wen-Zen Shen , Juinn-Dar Huang , Shih-Min Chao, Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.65-69, June 12-16, 1995, San Francisco, California, United States
	Peichen Pan , Chih-Chang Lin, A new retiming-based technology mapping algorithm for LUT-based FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.35-42, February 22-25, 1998, Monterey, California, United States
	Peichen Pan , C. L. Liu, Optimal clock period FPGA technology mapping for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.437-462, July 1998
	Shigeru Yamashita , Hiroshi Sawada , Akira Nagoya, A new method to express functional permissibilities for LUT based FPGAs and its applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.254-261, November 10-14, 1996, San Jose, California, United States
	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Peichen Pan , C. L. Liu, Technology mapping of sequential circuits for LUT-based FPGAs for performance, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.58-64, February 11-13, 1996, Monterey, California, United States
	Chau-Shen Chen , Yu-Wen Tsay , TingTing Hwang , Allen C. H. Wu , Youn-Long Lin, Combining technology mapping and placement for delay-optimization in FPGA designs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.123-127, November 07-11, 1993, Santa Clara, California, United States
	Kevin Karplus, Amap: A technology mapper for selector-based field-programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.244-247, June 17-22, 1991, San Francisco, California, United States
	Wei Wan , Marek A. Perkowski, A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping, Proceedings of the conference on European design automation, p.230-235, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Peichen Pan , C. L. Liu, Optimal clock period FPGA technology mapping for sequential circuits, Proceedings of the 33rd annual conference on Design automation, p.720-725, June 03-07, 1996, Las Vegas, Nevada, United States
	P. Sawkar , D. Thomas, Area and delay mapping for table-look-up based field programmable gate arrays, Proceedings of the 29th ACM/IEEE conference on Design automation, p.368-373, June 08-12, 1992, Anaheim, California, United States
	Robert J. Francis, A tutorial on logic synthesis for lookup-table based FPGAs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.40-47, November 1992, Santa Clara, California, United States
	Juinn-Dar Huang , Jing-Yang Jou , Wen-Zen Shen, Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.359-363, November 05-09, 1995, San Jose, California, United States
	Kuang-Chien Chen , Jason Cong, Maximal reduction of lookup-table based FPGAs, Proceedings of the conference on European design automation, p.224-229, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Bernd Wurth , Ulf Schlichtmann , Klaus Eckl , Kurt J. Antreich, Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.3, p.313-350, July 1999
	Zafar Hasan , David Harrison , Maciej Ciesielski, A Fast Partitioning Method for PLA-Based FPGAs, IEEE Design & Test, v.9 n.4, p.34-39, October 1992
	Kuang-Chien Chen , Jason Cong , Yuzheng Ding , Andrew B. Kahng , Peter Trajmar, DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization, IEEE Design & Test, v.9 n.3, p.7-20, July 1992
	Hao Li , Srinivas Katkoori , Wai-Kei Mak, Power minimization algorithms for LUT-based FPGA technology mapping, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.1, p.33-51, January 2004
	Navin Vemuri , Priyank Kalla , Russell Tessier, BDD-based logic synthesis for LUT-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.501-525, October 2002
	Mark Kahrs , Bart N. Locanthi , Robert C. Restrick III, Technology Mapping in Circuit Design Aids, IEEE Design & Test, v.11 n.3, p.39-47, July 1994
	Hao Li , Wai-Kei Mak , Srinivas Katkoori, Efficient LUT-based FPGA technology mapping for power minimization, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Jason Cong , Kirill Minkovich, Optimality study of logic synthesis for LUT-based FPGAs, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	M. Teslenko , E. Dubrova, Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.748-751, November 07-11, 2004
	D. Chen , J. Cong, DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.752-759, November 07-11, 2004
	Min Xu , Fadi Kurdahi, Area and Timing Estimation for Lookup Table Based FPGAs, Proceedings of the 1996 European conference on Design and Test, p.151, March 11-14, 1996