Technology mapping for electrically programmable gate arrays

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Technology mapping for electrically programmable gate arrays

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 234 - 239

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Silvia Ercolani	Center for Integrated Systems, Stanford University, Stanford, CA
Giovanni De Micheli	Center for Integrated Systems, Stanford University, Stanford, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 13, Citation Count: 16

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. El Gamal, J. Greene, J. Reynery, E. Rogoyski, K.A. El Ayat, and A. Mohsen, "Architecture for Electrically Configurable Gate Arrays", IEEE Journal of Solid-State Circuits, April 1989, pp. 394- 398
	2	Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123421]
	3	R~. Brayton, R. Rudell, A. Sangiovanni-Vineentelli, and A.R. Wang, '~MIS: A Multiple-Level Logic Optimization System", IEEE Transactions on CAD, November 1987, pp. 1062-1081
	4	Frédéric Mailhot , Giovanni De Micheli, Technology mapping using boolean matching and don't care sets, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	5	J. Rose, R. Francis, D. Lewis and P. Chow, "Architecture of Field Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency", IEEE Journal of Solid State Circuits, Vol. 25, No_5, October 1990, pp. 1217-1225
	6	K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37940]
	7	Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989
	8	E. Detjens, G. Gannot, R.L. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang. "Technology mapping in rnis", International Conference on Computer-Aided Design, November 1987, pp. 116-119
	9	S.B. Akers, "Binary Decision Diagrams", IEEE Transactions on Computer, June 1978, pp. 509-516
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	11	Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123222]

CITED BY 16

	R. Murgai , R. K. Brayton , A. L. Sangiovanni-Vincentelli, An improved synthesis algorithm for multiplexor-based PGA's, Proceedings of the 29th ACM/IEEE conference on Design automation, p.380-386, June 08-12, 1992, Anaheim, California, United States
	Mahesh Mehendale, MIM: logic module independent technology mapping for design and evaluation of antifuse-based FPGAs, Proceedings of the 30th international conference on Design automation, p.219-223, June 14-18, 1993, Dallas, Texas, United States
	Shashidhar Thakur , D. F. Wong, On designing ULM-based FPGA logic modules, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.3-9, February 12-14, 1995, Monterey, California, United States
	K. Chung , J. Rose, TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections, Proceedings of the 29th ACM/IEEE conference on Design automation, p.361-367, June 08-12, 1992, Anaheim, California, United States
	D. D. Hill , E. Detjens, FPGA design principles (a tutorial), Proceedings of the 29th ACM/IEEE conference on Design automation, p.45-46, June 08-12, 1992, Anaheim, California, United States
	Sudip K. Nag , Rob A. Rutenbar, Performance-driven simultaneous place and route for row-based FPGAs, Proceedings of the 31st annual conference on Design automation, p.301-307, June 06-10, 1994, San Diego, California, United States
	U. Schlichtmann , F. Brglez , M. Hermann, Characterization of Boolean functions for rapid matching in FPGA technology mapping, Proceedings of the 29th ACM/IEEE conference on Design automation, p.374-379, June 08-12, 1992, Anaheim, California, United States
	Sudip K. Nag , Rob A. Rutenbar, Performance-driven simultaneous place and route for island-style FPGAs, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.332-338, November 05-09, 1995, San Jose, California, United States
	Jerry R. Burch , David E. Long, Efficient Boolean function matching, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.408-411, November 1992, Santa Clara, California, United States
	Luca Benini , Giovanni De Micheli, A survey of Boolean matching techniques for library binding, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.3, p.193-226, July 1997
	Sudip Nag , Kaushik Roy, On Routability for FPGAs under Faulty Conditions, IEEE Transactions on Computers, v.44 n.11, p.1296-1305, November 1995
	Debatosh Debnath , Tsutomu Sasao, Efficient computation of canonical form for Boolean matching in large libraries, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.591-596, January 27-30, 2004, Yokohama, Japan
	Mark Kahrs , Bart N. Locanthi , Robert C. Restrick III, Technology Mapping in Circuit Design Aids, IEEE Design & Test, v.11 n.3, p.39-47, July 1994
	Cheng-Hsing Yang , Chia-Chun Tsai , Jan-Ming Ho , Sao-Jie Chen, Hmap: a fast mapper for EPGAs using extended GBDD hash tables, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.135-150, April 1997
	B. Kapoor, Improved technology mapping using a new approach to Boolean matching, Proceedings of the 1995 European conference on Design and Test, p.86, March 06-09, 1995
	Rüdiger Ebendt , Rolf Drechsler, Weighted A∗ search -- unifying view and application, Artificial Intelligence, v.173 n.14, p.1310-1342, September, 2009