Breaking the barrier of parallel simulation of digital systems

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Breaking the barrier of parallel simulation of digital systems

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 223 - 226

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Jack V. Briner, Jr.	Department of Mathematics, University of North Carolina at Greensboro, Greensboro, NC
John L. Ellis	Department of Computer Science, Duke University, Durham, NC
Gershon Kedem	Department of Computer Science, Duke University, Durham, NC

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 12, Citation Count: 13

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Arnold, J., Parallel Simulation of Digital Circuits, Master's Thesis, Massachusetts Institute of Technology, 1985.
	2	Mary L. Bailey , Lawrence Snyder, An empirical study of on-chip parallelism, Proceedings of the 25th ACM/IEEE conference on Design automation, p.160-165, June 12-15, 1988, Atlantic City, New Jersey, United States
	3	Briner, L, "A framework for analyzing parallel discrete event simulation", Proc. of the Computer Measurement Group, 1988.
	4	Briner, J., Ellis, J. and Kedem, G., "Taking advantage of optimal on-chip parallelism for parallel discrete event simulation", Intl. Conf. on Computer Aided Design, 1988.
	5	Briner, J., Ellis, J. and Kedem, G., "Parallel mixed-level simulation using virtual time", Proc. of the lnt.Workshop on CAD Accelerators, Oxford, September 1989.
	6	Briner, J., Ellis, J. and Kedem, G., "Leonardo: A mixed level system simulator", Proc. of the Pittsburgh Simulation Conf., 1990.
	7	Jack Vedder Briner, Jr. , Gershon Kedem , John L. Ellis, Parallel mixed-level simulation of digital circuits using virtual time, 1990
	8	David R. Jefferson, Virtual time, ACM Transactions on Programming Languages and Systems (TOPLAS), v.7 n.3, p.404-425, July 1985 [doi>10.1145/3916.3988]
	9	Kedem, 13. and Ellis, J., "The ray-casting machine", in Parallel Processing for Computer Vision and Display, P. M. Dow, R. A. Earnshawand and T. R. Heywood, Eds., Addison- Wesley, Reading, MA, 1988.
	10	Roy, S., A Testable CMOS QRS Detector and Arrythmia Monitor, Master's Thesis, University of North Carolina, Chapel Hill, 1990.
	11	Terman, C. J., Simulation Tools for Digital LSI Design, Ph. D. Dissertation, Massachusetts Institute of Technology, 1983.
	12	Larry Soulé , Tom Blank, Parallel logic simulation on general purpose machines, Proceedings of the 25th ACM/IEEE conference on Design automation, p.166-171, June 12-15, 1988, Atlantic City, New Jersey, United States
	13	L. Soule , A. Gupta, Characterization of parallelism and deadlocks in distributed digital logic simulation, Proceedings of the 26th ACM/IEEE conference on Design automation, p.81-86, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74397]
	14	K. F. Wong , M. A. Franklin , R. D. Chamberlain , B. L. Shing, Statistics on logic simulation, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.13-19, July 1986, Las Vegas, Nevada, United States

CITED BY 13

	Larry Soulé , Anoop Gupta, An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation, ACM Transactions on Modeling and Computer Simulation (TOMACS), v.1 n.4, p.308-347, Oct. 1991
	Rajive Bagrodia , Zheng Li , Vikas Jha , Yuan Chen , Jason Cong, Parallel logic level simulation of VLSI circuits, Proceedings of the 26th conference on Winter simulation, p.1354-1361, December 11-14, 1994, Orlando, Florida, United States
	Antonio R. W. Todesco , Teresa H.-Y. Meng, Symphony: a simulation backplane for parallel mixed-mode co-simulation of VLSI systems, Proceedings of the 33rd annual conference on Design automation, p.149-154, June 03-07, 1996, Las Vegas, Nevada, United States
	Rajive Bagrodia , Yu-an Chen , Vikas Jha , Nicki Sonpar, Parallel gate-level circuit simulation on shared memory architectures, ACM SIGSIM Simulation Digest, v.25 n.1, p.170-174, July 1995
	Roger D. Chamberlain, Parallel logic simulation of VLSI systems, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.139-143, June 12-16, 1995, San Francisco, California, United States
	Naraig Manjikian , Wayne M. Loucks, High performance parallel logic simulations on a network of workstations, ACM SIGSIM Simulation Digest, v.23 n.1, p.76-84, July 1993
	Mary L. Bailey , Jack V. Briner, Jr. , Roger D. Chamberlain, Parallel logic simulation of VLSI systems, ACM Computing Surveys (CSUR), v.26 n.3, p.255-294, Sept. 1994
	Chih-Po Wen , Katherine A. Yelick, Parallel timing simulation on a distributed memory multiprocessor, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.130-135, November 07-11, 1993, Santa Clara, California, United States
	Rajive L. Bagrodia, Language support for parallel discrete-event simulations, Proceedings of the 26th conference on Winter simulation, p.1324-1331, December 11-14, 1994, Orlando, Florida, United States
	Sumit Ghosh, P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors, IEEE Transactions on Computers, v.50 n.1, p.28-50, January 2001
	Rajive L. Bagrodia, Parallel Languages for Discrete-Event Simulation Models, IEEE Computational Science & Engineering, v.5 n.2, p.27-38, April 1998
	Sumit Ghosh , Meng-Lin Yu, An Asynchronous Distributed Approach for the Simulation of Behavior-Level Models on Parallel Processors, IEEE Transactions on Parallel and Distributed Systems, v.6 n.6, p.639-652, June 1995
	P. Walker , S. Ghosh, Exploiting temporal independence in distributed preemptive circuit simulation, Proceedings of the 1997 European conference on Design and Test, p.378, March 17-20, 1997