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Automatic generation of compiled simulations through program specialization
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents
San Francisco, California, United States
Pages: 205 - 210  
Year of Publication: 1991
ISBN:0-89791-395-7
Authors
Wing Yee Au  Computer Systems Laboratory, Stanford University, Stanford, CA
Daniel Weise  Computer Systems Laboratory, Stanford University, Stanford, CA
Scott Seligman  Computer Systems Laboratory, Stanford University, Stanford, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 5,   Citation Count: 4
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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D. M. Lewis, "Hierarchical Compiled Event-Driven Logic Simulation," Proceedings of ICCAD-89, pp. 498- 500.
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Z. Barzilai, 3. L. Carter, B. K. Rosen, J. D. Rutledge, "HSS-A High-Speed Simulator," IEEE Trans. on Computer-Aided Design, 6(4), July, 1987, pp. 601-16.
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D. Weise, Hierarchical Formal Multilevel Verification of Digital MOS/VLSI Circuits, PhD. Thesis, Massachusetts Institute of Technology, Artificial Intelligence Laboratory Technical Report 978, Cambridge, MA, 1984.
 
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D. Weise, "Graphs as an Intermediate Representation for Partial Evaluation," Stanford University, Computer System Laboratory Technical Report CSL-TR-90-421, Stanford, CA, 1990.
 
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Brglez, Franc, P. Pownall, R. Hum, "Accelerated ATPG and Fault Grading Via Testability Analysis," Proceedings of the International Symposium on Circuit and Systems, 1985.


Collaborative Colleagues:
Wing Yee Au: colleagues
Daniel Weise: colleagues
Scott Seligman: colleagues