| Automatic generation of compiled simulations through program specialization |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 28th ACM/IEEE Design Automation Conference
table of contents
San Francisco, California, United States
Pages: 205 - 210
Year of Publication: 1991
ISBN:0-89791-395-7
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Authors
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Wing Yee Au
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Computer Systems Laboratory, Stanford University, Stanford, CA
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Daniel Weise
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Computer Systems Laboratory, Stanford University, Stanford, CA
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Scott Seligman
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Computer Systems Laboratory, Stanford University, Stanford, CA
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| Bibliometrics |
Downloads (6 Weeks): 6, Downloads (12 Months): 9, Citation Count: 4
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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D. M. Lewis, "Hierarchical Compiled Event-Driven Logic Simulation," Proceedings of ICCAD-89, pp. 498- 500.
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S. P. Smith , M. R. Mercer , B. Brodk, Demand driven simulation: BACKSIM, Proceedings of the 24th ACM/IEEE conference on Design automation, p.181-187, June 28-July 01, 1987, Miami Beach, Florida, United States
[doi> 10.1145/37888.37915]
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R. E. Bryant , D. Beatty , K. Brace , K. Cho , T. Sheffler, COSMOS: a compiled simulator for MOS circuits, Proceedings of the 24th ACM/IEEE conference on Design automation, p.9-16, June 28-July 01, 1987, Miami Beach, Florida, United States
[doi> 10.1145/37888.37890]
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Z. Barzilai, 3. L. Carter, B. K. Rosen, J. D. Rutledge, "HSS-A High-Speed Simulator," IEEE Trans. on Computer-Aided Design, 6(4), July, 1987, pp. 601-16.
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D. Weise, Hierarchical Formal Multilevel Verification of Digital MOS/VLSI Circuits, PhD. Thesis, Massachusetts Institute of Technology, Artificial Intelligence Laboratory Technical Report 978, Cambridge, MA, 1984.
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D. Weise, "Graphs as an Intermediate Representation for Partial Evaluation," Stanford University, Computer System Laboratory Technical Report CSL-TR-90-421, Stanford, CA, 1990.
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Brglez, Franc, P. Pownall, R. Hum, "Accelerated ATPG and Fault Grading Via Testability Analysis," Proceedings of the International Symposium on Circuit and Systems, 1985.
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