A CAD system for the design of field programmable gate arrays

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A CAD system for the design of field programmable gate arrays

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 187 - 192

Year of Publication: 1991

ISBN:0-89791-395-7

Author

Dwight D. Hill

AT&T Bell Laboratories, Murray Hill, New Jersey

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 10, Citation Count: 10

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	2	S. Brown, J. Rose, and Z. Vranesic. A detailed router for field-programmable gate arrays. Proc ICCAD, pages 382- 385, Nov. 1990.
	3	Robert J. Francis , Jonathan Rose , Kevin Chung, Chortle: a technology mapping program for lookup table-based field programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.613-619, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123418]
	4	Jonathan Greene , Vwani Roychowdhury , Sinan Kaptanoglu , Abbas El Gamal, Segmented channel routing, Proceedings of the 27th ACM/IEEE conference on Design automation, p.567-572, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123405]
	5	D. Hill and D. Cassiday. Preliminary description of tabula rasa: An electrically reconfigurable hardware engine. International Conference on Computer and Design, 1990.
	6	Dwight D. Hill , Kurt Keutzer , Don Shugard , John Fishburn, Algorithms and Techniques for VLSI Layout and Synthesis, Kluwer Academic Publishers, Norwell, MA, 1988
	7	MCNC and U. of California, Berkeley. Logic Synthesis and Optimization Benchmarks User Guide, Version 3.0. MCNC, 1991.
	8	J. Rose and S. Brown. Flexibility of interconnection structures in field-programmable gate arrays. IEEE Journal of Solid State Circuits, 26(3):277-282, March 1990.
	9	Nam-Sung Woo, A heuristic method for FPGA technology mapping based on the edge visibility, Proceedings of the 28th conference on ACM/IEEE design automation, p.248-251, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127675]
	10	Xilinx Corporation. Xilinx Programmable Gate Array User's Guide. Xilinx, 1988.
	11	Xilinx Corporation. Technical Data Book: XC 4000 Logic Cell Array Family. Xilinx, 1990.

CITED BY 10

	Jason Cong , Yuzheng Ding, An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.48-53, November 1992, Santa Clara, California, United States
	D. D. Hill , E. Detjens, FPGA design principles (a tutorial), Proceedings of the 29th ACM/IEEE conference on Design automation, p.45-46, June 08-12, 1992, Anaheim, California, United States
	Vijay Lakamraju , Russell Tessier, Tolerating operational faults in cluster-based FPGAs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.187-194, February 10-11, 2000, Monterey, California, United States
	Jason Cong , Yuzheng Ding, On nominal delay minimization in LUT-based FPGA technology mapping, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.82-88, February 12-14, 1995, Monterey, California, United States
	Jason Cong , Yuzheng Ding, On area/depth trade-off in LUT-based FPGA technology mapping, Proceedings of the 30th international conference on Design automation, p.213-218, June 14-18, 1993, Dallas, Texas, United States
	Darren C. Cronquist , Larry McMurchie, Emerald: an architecture-driven tool compiler for FPGAs, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.144-150, February 11-13, 1996, Monterey, California, United States
	Kuang-Chien Chen , Jason Cong, Maximal reduction of lookup-table based FPGAs, Proceedings of the conference on European design automation, p.224-229, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Larry McMurchie , Carl Ebeling, PathFinder: a negotiation-based performance-driven router for FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.111-117, February 12-14, 1995, Monterey, California, United States
	Kuang-Chien Chen , Jason Cong , Yuzheng Ding , Andrew B. Kahng , Peter Trajmar, DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization, IEEE Design & Test, v.9 n.3, p.7-20, July 1992
	M. Palczewski, Plane parallel a maze router and its application to FPGAs, Proceedings of the 29th ACM/IEEE conference on Design automation, p.691-697, June 08-12, 1992, Anaheim, California, United States