On removing redundancy in sequential circuits

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On removing redundancy in sequential circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 164 - 169

Year of Publication: 1991

ISBN:0-89791-395-7

Author

Kwang-Ting Cheng

AT&T Bell Laboratories, Murray Hill, NJ

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 18, Citation Count: 16

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Abramovici and M. A. Breuer, "On Redundancy and Fault Detection in Sequential Circuits," IEEE Trans. on Computers C-28, pp. 864-865 (November 1979).
	2	Srinivas Devadas , Hi-Keung Y. Ma , A. Richard Newton, Redundancies and don't cares in sequential logic synthesis, Journal of Electronic Testing: Theory and Applications, v.1 n.1, p.15-30, Feb. 1990 [doi>10.1007/BF00134012]
	3	S. Malik, E. M. Sentovich, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques," Proc. lnt'l Workshop on Logic Synthesis (May 1989).
	4	M. Damiani and G. De Micheli, "Synchronous Logic Synthesis: Circuit Specifications and Optimization Algorithms " Proc. Int'l Syrup. on Circuits and Systems, pp. 2556- 2570 (May 1990).
	5	A Miczo, Digital logic testing and simulation, Harper & Row Publishers, Inc., New York, NY, 1985
	6	F. Brglez, D. Bryan, and K. Kozaninski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. int'l Syrup. on Circuits and Systems, pp. 1929-1934 (May 1989).
	7	H.-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovanni-Vincentelli, "Test Generation for Sequential Circuits," IEEE Trans. on CAD 7, pp. 1081-1093 (October 1988).
	8	A. Ghosh, S. Devadas, and A. R. Newton, "Test Generation for Highly Sequential Circuits," Int'l Conference on Computer-Aided Design, pp. 362-365 (Nov. 1989).
	9	H. Kubo, "A Procedure for Generating Test Sequences to Detect Sequential Circuit Failures," NEC Res. & Dev., pp. 69-78 (October 1968).
	10	G.R. Putzolu and J. P. Roth, "A Heuristic Algorithm for the Testing of Asynchronous Circuits," IEEE Trans. Computers C-20, pp. 639-647 (June 1971).
	11	Kwang-Ting Cheng , Vishwani D. Agrawal, Unified Methods for VLSI Simulation and Test Generation, Kluwer Academic Publishers, Norwell, MA, 1989
	12	Ralph A. Marlett, EBT: A comprehensive test generation technique for highly sequential circuits, Proceedings of the 15th conference on Design automation, p.335-339, June 19-21, 1978, Las Vegas, Nevada, United States
	13	W.T. Cheng, "The BACK Algorithm for Sequential Test Generation," Proc. Int. Conf. Computer Design (ICCD- 88), Rye Brook, NY, pp. 66-69 (October 1988).
	14	W.-T. Cheng, Private Communication.
	15	M. Abramovici, M. A. Breuer, and A. D. Friedman, Digi. tal Systems Testing and Testable Design, Computer Science Press (1990).
	16	K.T. Cheng and V. D. Agrawal, "State Assignment for Initializable Synthesis," Int'l Conf. on Computer-Aided Design (ICCAD-89), pp. 212-215 (Nov. 1989).
	17	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	18	R.M. Karp, "Reducibility between combinatorial problems," Plenum Press, pp. 85-103 (1972). Complexity of Computer Computations, R.E. Miller and J. W. Thatcher, Eds.
	19	J.C. Tieman, "An Efficient Search Algorithm to Find the Elementary Circuits of a Graph," J. ACM 32-2, pp. 296- 313 (April 1985).
	20	D.H. Lee and S. M. Reddy, "On Determining Scan Flip- Flops in Partial-Scan Designs," Int'l Conf. on Computer. Aided Design (ICCAD-90) (Nov. 1990).
	21	R. Gupta , M. A. Breuer, The Ballast Methodology for Structured Partial Scan Design, IEEE Transactions on Computers, v.39 n.4, p.538-544, April 1990 [doi>10.1109/12.54846]
	22	W.-T. Cheng and S. Davidson, "Sequential Circuit Test Generator (STG) Benchmark Results," Proc. Int'l Symp. on Circuits and Systems, pp. 1939-1941 (May 1989).

CITED BY 16

	Ellen Sentovich , Daniel Brand, Flexibillity in logic, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	K.-T. Cheng , H.-K. T. Ma, On the over-specification problem in sequential ATPG algorithms, Proceedings of the 29th ACM/IEEE conference on Design automation, p.16-21, June 08-12, 1992, Anaheim, California, United States
	Wanlin Cao , Dhiraj K. Pradhan, Sequential redundancy identification using recursive learning, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.56-62, November 10-14, 1996, San Jose, California, United States
	Huey-Yih Wang , Robert K. Brayton, Multi-level logic optimization of FSM networks, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.728-735, November 05-09, 1995, San Jose, California, United States
	Mahesh A. Iyer , David E. Long , Miron Abramovici, Identifying sequential redundancies without search, Proceedings of the 33rd annual conference on Design automation, p.457-462, June 03-07, 1996, Las Vegas, Nevada, United States
	Fabrizio Ferrandi , Franco Fummi , Donatella Sciuto , Enrico Macii , Massimo Poncino, Testing Core-Based Systems: A Symbolic Methodology, IEEE Design & Test, v.14 n.4, p.69-77, October 1997
	I. Pomeranz , S. M. Reddy, Classification of Faults in Synchronous Sequential Circuits, IEEE Transactions on Computers, v.42 n.9, p.1066-1077, September 1993
	Luis Entrena , Kwang-Ting Cheng, Sequential logic optimization by redundancy addition and removal, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.310-315, November 07-11, 1993, Santa Clara, California, United States
	Franco Fummi , Donatella Sciuto , Micaela Serra, Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal, IEEE Transactions on Computers, v.48 n.12, p.1305-1323, December 1999
	Irith Pomeranz , Sudhakar M. Reddy, On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences, IEEE Transactions on Computers, v.45 n.1, p.20-32, January 1996
	Franco Fummi , Donatella Sciuto, A Hierarchical Test Generation Approach for Large Controllers, IEEE Transactions on Computers, v.49 n.4, p.289-302, April 2000
	Irith Pomeranz , Sudhakar M. Reddy, On undetectable faults in partial scan circuits, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.82-86, November 10-14, 2002, San Jose, California
	Hsing-chung Liang , Chung Len Lee , Jwu E. Chen, Identifying Untestable Faults in Sequential Circuits, IEEE Design & Test, v.12 n.3, p.14-23, September 1995
	Debesh K. Das , Uttam K. Bhattacharya , Bhargab B. Bhattacharya, Isomorph-Redundancy in Sequential Circuits, IEEE Transactions on Computers, v.49 n.9, p.992-997, September 2000
	Enrique San Millán , Luis Entrena , José A. Espejo , Silvia Chiusano , Fulvio Corno, Integrating symbolic techniques in ATPG-based sequential logic optimization, Proceedings of the conference on Design, automation and test in Europe, p.105-es, January 1999, Munich, Germany
	Mahesh A. Iyer , David E. Long , Miron Abramovici, Surprises in Sequential Redundancy Identification, Proceedings of the 1996 European conference on Design and Test, p.88, March 11-14, 1996