Layout driven technology mapping

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Layout driven technology mapping

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 99 - 105

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Massoud Pedram	Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA
Narasimha Bhat	Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 37, Citation Count: 39

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	15	M. Pedram and B. T. Preas, "Interconnection length estimation for optimized standard cell layouts," Proc. Int. Conf. CAD (ICCAD-89), pp. 390-393, 1989.
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	Sasan Iman , Massoud Pedram , Kamal Chaudhary, Technology mapping using fuzzy logic, Proceedings of the 31st annual conference on Design automation, p.333-338, June 06-10, 1994, San Diego, California, United States
	Aiguo Lu , Guenter Stenz , Frank M. Johannes, Technology mapping for minimizing gate and routing area, Proceedings of the conference on Design, automation and test in Europe, p.664-669, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Victor N. Kravets , Karem A. Sakallah, M32: a constructive multilevel logic synthesis system, Proceedings of the 35th annual conference on Design automation, p.336-341, June 15-19, 1998, San Francisco, California, United States
	Jinan Lou , Amir H. Salek , Massoud Pedram, An exact solution to simultaneous technology mapping and linear placement problem, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.671-675, November 09-13, 1997, San Jose, California, United States
	Hsiao-Pin Su , Allen C.-H. Wu , Youn-Long Lin, A timing-driven soft-macro resynthesis method in interaction with chip floorplanning, Proceedings of the 36th ACM/IEEE conference on Design automation, p.262-267, June 21-25, 1999, New Orleans, Louisiana, United States
	Huiqun Liu , D. F. Wong, Network flow based circuit partitioning for time-multiplexed FPGAs, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.497-504, November 08-12, 1998, San Jose, California, United States
	K. Chaudhary , M. Pedram, A near optimal algorithm for technology mapping minimizing area under delay constraints, Proceedings of the 29th ACM/IEEE conference on Design automation, p.492-498, June 08-12, 1992, Anaheim, California, United States
	Koichi Sato , Masamichi Kawarabayashi , Hideyuki Emura , Naotaka Maeda, Post-layout optimization for deep submicron design, Proceedings of the 33rd annual conference on Design automation, p.740-745, June 03-07, 1996, Las Vegas, Nevada, United States
	T. Mitsuhashi , M. Murakata , K. Yoshida , T. Aoki, Physical design CAD in deep sub-micron era, Proceedings of the conference on European design automation, p.350-355, September 1996, Geneva, Switzerland
	Hirendu Vaishnav , Massoud Pedram, Routability-driven fanout optimization, Proceedings of the 30th international conference on Design automation, p.230-235, June 14-18, 1993, Dallas, Texas, United States
	Guenter Stenz , Bernhard M. Riess , Bernhard Rohfleisch , Frank M. Johannes, Timing driven placement in interaction with netlist transformations, Proceedings of the 1997 international symposium on Physical design, p.36-41, April 14-16, 1997, Napa Valley, California, United States
	Jason Cong , Songjie Xu, Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs, Proceedings of the 2000 conference on Asia South Pacific design automation, p.157-162, January 2000, Yokohama, Japan
	Olivier Coudert, Logical and physical design: a flow perspective, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Masako Murofushi , Takashi Ishioka , Masami Murakata , Takashi Mitsuhashi, Layout driven re-synthesis for low power consumption LSIs, Proceedings of the 34th annual conference on Design automation, p.666-669, June 09-13, 1997, Anaheim, California, United States
	Shih-Chieh Chang , Jung-Cheng Chuang , Zhong-Zhen Wu, Synthesis for multiple input wires replacement of a gate for wiring consideration, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.115-119, November 07-11, 1999, San Jose, California, United States
	Leon Stok , Vivek Tiwari, Technology mapping, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Hamid Savoj , Mário J. Silva , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Boolean matching in logic synthesis, Proceedings of the conference on European design automation, p.168-174, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Lalgudi N. Kannan , Peter R. Suaris , Hong-Gee Fang, A methodology and algorithms for post-placement delay optimization, Proceedings of the 31st annual conference on Design automation, p.327-332, June 06-10, 1994, San Diego, California, United States
	Champaka Ramachandran , Fadi J. Kurdahi, Combined topological and functionality based delay estimation using a layout-driven approach for high level applications, Proceedings of the conference on European design automation, p.72-78, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	Glenn Holt , Akhilesh Tyagi, Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis, Proceedings of the 1997 international symposium on Physical design, p.48-53, April 14-16, 1997, Napa Valley, California, United States
	Yanbin Jiang , Sachin S. Sapatnekar, An integrated algorithm for combined placement and libraryless technology mapping, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.102-106, November 07-11, 1999, San Jose, California, United States
	Olivier Coudert , Jason Cong , Sharad Malik , Majid Sarrafzadeh, Incremental CAD, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Wilsin Gosti , Sunil P. Khatri , Alberto L. Sangiovanni-Vincentelli, Addressing the timing closure problem by integrating logic optimization and placement, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Qinghua Liu , Malgorzata Marek-Sadowska, A study of netlist structure and placement efficiency, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Tzu-Chieh Tien , Hsiao-Pin Su , Yu-Wen Tsay , Yih-Chih Chou , Youn-Long Lin, Integrating logic retiming and register placement, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.136-139, November 08-12, 1998, San Jose, California, United States
	Wilsin Gosti , Amit Narayan , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Wireplanning in logic synthesis, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.26-33, November 08-12, 1998, San Jose, California, United States
	Qinghua Liu , Malgorzata Marek-Sadowska, Pre-layout wire length and congestion estimation, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Ankur Srivastava , Ryan Kastner , Chunhong Chen , Majid Sarrafzadeh, Timing driven gate duplication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.42-51, January 2004
	Rupesh S. Shelar , Prashant Saxena , Xinning Wang , Sachin S. Sapatnekar, An efficient technology mapping algorithm targeting routing congestion under delay constraints, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Qinghua Liu , Malgorzata Marek-Sadowska, Wire length prediction-based technology mapping and fanout optimization, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Majid Sarrafzadeh , Wei-Liang Lin , C. K. Wong, Floating Steiner Trees, IEEE Transactions on Computers, v.47 n.2, p.197-211, February 1998
	Davide Pandini , Lawrence T. Pileggi , Andrzej J. Strojwas, Bounding the efforts on congestion optimization for physical synthesis, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Davide Pandini , Lawrence T. Pileggi , Andrzej J. Strojwas, Understanding and addressing the impact of wiring congestion during technology mapping, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	S. Chatterjee , R. Brayton, A new incremental placement algorithm and its application to congestion-aware divisor extraction, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.541-548, November 07-11, 2004
	Prashant Saxena , Vishal Khandelwal , Changge Qiao , Pei-Hsin Ho , J.-C. Lin , Mahesh A. Iyer, On improving optimization effectiveness in interconnect-driven physical synthesis, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA
	Yifang Liu , Rupesh S. Shelar , Jiang Hu, Delay-optimal simultaneous technology mapping and placement with applications to timing optimization, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Jae-sun Seo , Igor L. Markov , Dennis Sylvester , David Blaauw, On the decreasing significance of large standard cells in technology mapping, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California