An analytic net weighting approach for performance optimization in circuit placement

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An analytic net weighting approach for performance optimization in circuit placement

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 620 - 625

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Ren-Song Tsay	IBM T. J. Watson Research Center, Yorktown Heights, NY
Juergen Koehl	IBM Development Laboratory, D-7030 Boeblingen, Germany

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 21, Citation Count: 20

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael Burstein , Mary N. Youssef, Timing influenced layout design, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.124-130, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317845]
	2	C-K. Cheng and E. S. Kuh. Module placement based on resistive network optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-3(3):218-225, July 1984.
	3	A. E. Dunlop , V. D. Agrawal , D. N. Deutsch , M. F. Jukl , P. Kozak , M. Wiesel, Chip layout optimization using critical path weighting, Proceedings of the 21st conference on Design automation, p.133-136, June 25-27, 1984, Albuquerque, New Mexico, United States
	4	G.H. Golub and C. F. Vanloan. Matrix Computations. Johns Hopkins University Press, Baltimore, 1983.
	5	Kenneth M. Hall. An r-dimensional quadratic placement algorithm. Management Science, 17(3):219- 229, November 1970.
	6	S. Kirkpatric, C. D. Gelatt Jr., and M. P. Vecchi. Optimization by simulated annealing. Science, 20(220):671-680, May 13 1983.
	7	J. M. Kleinhans, G. Sigl, and F. M. Johannes. Gordian: A new global optimization/rectangle dissection method for cell placement. In Digest of Technical Papers, IEEE Internatzonal Conference on Computer- Aided Design, pages 506-509, 1988.
	8	D. P. Lapotin and Y.-H. Chen. Early matching of system requirements and package capabilities. In Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, pages 394-397, 1989.
	9	Ulrich Lauther, A min-cut placement algorithm for general cell assemblies based on a graph representation, Proceedings of the 16th Conference on Design automation, p.1-10, June 25-27, 1979, San Diego, CA, United States
	10	D. G. Luenberger. Linear and Nonlinear Programming. Addison-Wesley, Reading, 1984.
	11	Ravi Nair, C. L. Berman, P. S/. Hauge, and E. J. Yoffa. Generation of performance constraints of layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-8:860-874, 1989.
	12	K. C. Saraswat and F. Mohammadi. Effect of scaling of interconnections on the time delay of VLSI circuits. IEEE Transactions on Electron Devices, ED- 29:645-650, 1982.
	13	H. Schettler et. al. A mainframe processor in CMOS technology with 0.5 mu channel length. In Proceedings of the ISSCC, pages 50-51, 1990.
	14	A. Srinivasan, M. A. B. Jackson, and E. S. Kuh. A fast algorithm for performance driven placement. In Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, pages 328- 331, 1990.
	15	S. Teig, R. L. Smith, and J. Seaton. Timing-driven layout of cell-based IC's. VLSI System's Design, pages 63-73, May 1986.
	16	Ren-Song Tsay , Ernest S. Kuh , Chi-Ping Hsu, PROUD: A Sea-Of-Gates Placement Algorithm, IEEE Design & Test, v.5 n.6, p.44-56, November 1988 [doi>10.1109/54.9271]

CITED BY 20

	Qinghua Liu , Bo Hu , Malgorzata Marek-Sadowska, Wire length prediction in constraint driven placement, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
	Bill Halpin , C. Y. Roger Chen , Naresh Sehgal, Timing driven placement using physical net constraints, Proceedings of the 38th conference on Design automation, p.780-783, June 2001, Las Vegas, Nevada, United States
	William Swartz , Carl Sechen, Timing driven placement for large standard cell circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.211-215, June 12-16, 1995, San Francisco, California, United States
	J. Frankle, Iterative and adaptive slack allocation for performance-driven layout and FPGA routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.536-542, June 08-12, 1992, Anaheim, California, United States
	Sung-Woo Hur , Tung Cao , Karthik Rajagopal , Yegna Parasuram , Amit Chowdhary , Vladimir Tiourin , Bill Halpin, Force directed mongrel with physical net constraints, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Adaptive delay estimation for partitioning-driven PLD placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.60-63, February 2003
	Karthik Rajagopal , Tal Shaked , Yegna Parasuram , Tung Cao , Amit Chowdhary , Bill Halpin, Timing driven force directed placement with physical net constraints, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Haoxing Ren , David Z. Pan , David S. Kung, Sensitivity guided net weighting for placement driven synthesis, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Jason Cong , Joseph R. Shinnerl , Min Xie , Tim Kong , Xin Yuan, Large-scale circuit placement, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.389-430, April 2005
	Ting-Yuan Wang , Jeng-Liang Tsai , Charlie Chung-Ping Chen, Sensitivity guided net weighting for placement driven synthesis, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Qinghua Liu , Bo Hu , Malgorzata Marek-Sadowska, Individual wire-length prediction with application to timing-driven placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1004-1014, October 2004
	Brent Goplen , Prashant Saxena , Sachin Sapatnekar, Net weighting to reduce repeater counts during placement, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Tim (Tianming) Kong, A novel net weighting algorithm for timing-driven placement, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.172-176, November 10-14, 2002, San Jose, California
	Wenting Hou , Xianlong Hong , Weimin Wu , Yici Cai, A path-based timing-driven quadratic placement algorithm, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Andrew B. Kahng , Stefanus Mantik , Igor L. Markov, Min-max placement for large-scale timing optimization, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	A. B. Kahng , Q. Wang, An analytic placer for mixed-size placement and timing-driven placement, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.565-572, November 07-11, 2004
	A. P. Hurst , P. Chong , A. Kuehlmann, Physical placement driven by sequential timing analysis, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.379-386, November 07-11, 2004
	Jason Cong , Tim Kong , Joseph R. Shinnerl , Min Xie , Xin Yuan, Large-Scale Circuit Placement: Gap and Promise, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.883, November 09-13, 2003
	Jason Cong , Michail Romesis , Min Xie, Optimality and Stability Study of Timing-Driven Placement Algorithms, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.472, November 09-13, 2003
	Andrew B. Kahng , Igor L. Markov , Sherief Reda, Boosting: Min-Cut Placement with Improved Signal Delay, Proceedings of the conference on Design, automation and test in Europe, p.21098, February 16-20, 2004