A fast physical constraint generator for timing driven layout

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A fast physical constraint generator for timing driven layout

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 626 - 631

Year of Publication: 1991

ISBN:0-89791-395-7

Author

W. K. Luk

IBM Thomas J. Watson Research Center, Yorktown Heights, NY

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 10, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	BurYou84	M. Burstein and M. N. Youssef, Timing influenced layout design, IBM Research Report, RC 10862 (#48565), 11/15/84.
	JepLukTang90	Donald W. Jepsen, Wing K. Luk and Donald T. Tang, Method of controlling RC delay for chip placement, IBM Invention Disclosure YO890-0052, 1990.
	DonEtal90	Wilm E. Donath , Reini J. Norman , Bhuwan K. Agrawal , Stephen E. Bello , Sang Yong Han , Jerome M. Kurtzberg , Paul Lowy , Roger I. McMillan, Timing driven placement using complete path delays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.84-89, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123232]
	DunEtal84	A. E. Dunlop , V. D. Agrawal , D. N. Deutsch , M. F. Jukl , P. Kozak , M. Wiesel, Chip layout optimization using critical path weighting, Proceedings of the 21st conference on Design automation, p.133-136, June 25-27, 1984, Albuquerque, New Mexico, United States
	HauNai87	P. S. Hauge, R. Nair and E. J. Yoffa, Circuit Placement for predictable performance, Proc. of International Conference on Computer Aided Design, pp. 88-91, 1987.
	HitSmi82	R. B. Hitchcock, Sr., G. L. Smith and D. D. Cheng, Timing analysis of computer hardware, IBM J. Res. Develop., Vol. 26, No. 1, pp. 100-108, 1982.
	JacKuh89	M. A. B. Jackson , E. S. Kuh, Performance-driven placement of cell based IC's, Proceedings of the 26th ACM/IEEE conference on Design automation, p.370-375, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74444]
	KerLin70	B. W. Kernighan and S. Lin, An Efficient :Heuristics for Partitioning Graphs, Bell System Technical Journal, 49, (2), pp. 291-307, 1970.
	KirGel83	S. Kirkpatrick, C. Gelatt Jr., and M. Vecchi, Optimization by simulated annealing, Science, Vol. 220, pp. 671-680, May 1983.
	LukTang90	W.K. Luk and D.T.Tang, Method of estimating net capacitance in RC constraint generation for timing driven layout, IBM Invention Disclosure YO890-0563, 1990.
	MarLin89	M. Marek-Sadowska and S.P. Lin, Timing driven placement, Proc. ICCAD 89, pp. 94-97, 1989.

CITED BY 10

	Noel Menezes , Satyamurthy Pullela , Lawrence T. Pileggi, Simultaneous gate and interconnect sizing for circuit-level delay optimization, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.690-695, June 12-16, 1995, San Francisco, California, United States
	J. Frankle, Iterative and adaptive slack allocation for performance-driven layout and FPGA routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.536-542, June 08-12, 1992, Anaheim, California, United States
	S. Kim , P. Banerjee , V. Chickermane , J. H. Patel, APT: an area-performance-testability driven placement algorithm, Proceedings of the 29th ACM/IEEE conference on Design automation, p.141-146, June 08-12, 1992, Anaheim, California, United States
	H. Chang , E. Shragowitz , J. Liu , H. Youssef , B. Lu , S. Sutanthavibul, Net criticality revisited: an effective method to improve timing in physical design, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Xiaojian Yang , Bo-Kyung Choi , Majid Sarrafzadeh, Timing-driven placement using design hierarchy guided constraint generation, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.177-180, November 10-14, 2002, San Jose, California
	Jason Cong , Joseph R. Shinnerl , Min Xie , Tim Kong , Xin Yuan, Large-scale circuit placement, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.389-430, April 2005
	Andrew B. Kahng , Stefanus Mantik , Igor L. Markov, Min-max placement for large-scale timing optimization, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Jason Cong , Tim Kong , Joseph R. Shinnerl , Min Xie , Xin Yuan, Large-Scale Circuit Placement: Gap and Promise, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.883, November 09-13, 2003
	Chi-Ming Tsai , Kun-Tien Kuo , Chyi-Hui Hong , Rung-Bin Lin, An Adaptive Interconnect-Length Driven Placer, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.393, January 07-11, 2002
	J. Y. Sayah , R. Gupta , D. D. Sherlekar , P. S. Honsinger , J. M. Apte , S. W. Bollinger , H. H. Chen , S. DasGupta , E. P. Hsieh , A. D. Huber , E. J. Hughes , Z. M. Kurzum , V. B. Rao , T. Tabtieng , V. Valijan , D. Y. Yang, Design planning for high-performance ASICs, IBM Journal of Research and Development, v.40 n.4, p.431-452, July 1996