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Testing patterns for software transactional memory engines
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International Symposium on Software Testing and Analysis archive
Proceedings of the 2007 ACM workshop on Parallel and distributed systems: testing and debugging table of contents
London, United Kingdom
SESSION: Bug patterns in MPD programs table of contents
Pages: 36 - 42  
Year of Publication: 2007
ISBN:978-1-59593-748-3
Authors
João Lourenço  Universidade Nova de Lisboa, Portugal
Gonçalo Cunha  Universidade Nova de Lisboa, Portugal
Sponsors
ACM: Association for Computing Machinery
SIGSOFT: ACM Special Interest Group on Software Engineering
Publisher
ACM  New York, NY, USA
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ABSTRACT

The emergence of multi-core processors is promoting the use of concurrency and multithreading. To raise the abstraction level of synchronization constructs is fundamental to ease the development of concurrent software, and Software Transactional Memory (STM) is a good approach towards such goal. However, execution environment issues such as the processor instruction set, caching policy, and memory model, may have strong influence upon the reliability of STM engines. This paper addresses the testing of STM engines aiming at improving their reliability and independence from execution environment. From our experience with porting and extending a specific STM engine, we report on some of the bugs found and synthesize some testing patterns that proved to be useful at testing STM engines.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
D. Dice, O. Shalev, and N. Shavit. Transactional locking ii. In Proc. of the 20th International Symposium on Distributed Computing (DISC 2006), pages 194--208, 2006.
 
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David Dice and Nir Shavit. What really makes transactions faster? In Proceedings of the First ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing. Jun 2006.
 
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Robert Ennals. Software transactional memory should not be obstruction-free. Technical Report IRC-TR-06-052, Intel Research Cambridge Tech Report, Jan 2006.
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R. M. Tomasulo. An efficient algorithm for exploiting multiple arithmetic units. IBM Journal of Research and Development, 11(1):25, 1967.

Collaborative Colleagues:
João Lourenço: colleagues
Gonçalo Cunha: colleagues