Automated design of application specific superscalar processors: an analytical approach

ABSTRACT

Analytical modeling is applied to the automated design of application-specific superscalar processors. Using an analytical method bridges the gap between the size of the design space and the time required for detailed cycle-accurate simulations. The proposed design framework takes as inputs the design targets (upper bounds on execution time, area, and energy), design alternatives, and one or more application programs. The output is the set of out-of-order superscalar processors that are Pareto-optimal with respect to performance-energy-area. The core of the new design framework is made up of analytical performance and energy activity models, and an analytical model-based design optimization process.

For a set of benchmark programs and a design space of 2000 designs, the design framework arrives at all performance-energy-area Pareto-optimal design points within 16 minutes on a 2 GHz Pentium-4. In contrast, it is estimated that a naíve cycle-accurate simulation-based exhaustive search would require at least two months to arrive at the Pareto-optimal design points for the same design space.

REFERENCES

• 1: IBM, "PowerPC 440 Processor Core," available at http://www-306.ibm.com/.
• 2: Thomas Martin Conte, Systematic computer architecture prototyping, University of Illinois at Urbana-Champaign, Champaign, IL, 1992
• 3: Vinod Kathail , Shail Aditya , Robert Schreiber , B. Ramakrishna Rau , Darren C. Cronquist , Mukund Sivaraman, PICO: Automatically Designing Custom Computers, Computer, v.35 n.9, p.39-47, September 2002 [doi>10.1109/MC.2002.1033026]
• 4: B. Kumar , E. S. Davidson, Computer system design using a hierarchical approach to performance evaluation, Communications of the ACM, v.23 n.9, p.511-521, Sept. 1980 [doi>10.1145/359007.359012]
• 5: M. Asghar Bhatti, Practical Optimization Methods: With Mathematica Applications, Springer-Verlag New York, Inc., Secaucus, NJ, 2000
• 6: S. Kirkpatrick, C. Gellat, and M. Vecchi, "Optimization by Simulated Annealing," Science, vol. 220--4598, 1983, pp. 671--680.
• 7: Erez Perelman , Greg Hamerly , Brad Calder, Picking Statistically Valid and Early Simulation Points, Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, p.244, September 27-October 01, 2003
• 8: Roland E. Wunderlich , Thomas F. Wenisch , Babak Falsafi , James C. Hoe, SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 9: L. Eeckhout, "Accurate Statistical Workload Modeling," PhD Thesis: University of Gent, 2002.
• 10: Sébastien Nussbaum , James E. Smith, Modeling Superscalar Processors via Statistical Simulation, Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, p.15-24, September 08-12, 2001
• 11: Mark Oskin , Frederic T. Chong , Matthew Farrens, HLS: combining statistical and symbolic simulation to guide microprocessor designs, Proceedings of the 27th annual international symposium on Computer architecture, p.71-82, June 2000, Vancouver, British Columbia, Canada
• 12: Pierre Michaud , André Seznec , Stéphan Jourdan, An exploration of instruction fetch requirement in out-of-order superscalar processors, International Journal of Parallel Programming, v.29 n.1, p.35-58, 2001 [doi>10.1023/A:1026431920605]
• 13: Derek B. Noonburg , John P. Shen, Theoretical modeling of superscalar processor performance, Proceedings of the 27th annual international symposium on Microarchitecture, p.52-62, November 30-December 02, 1994, San Jose, California, United States [doi>10.1145/192724.192730]
• 14: E. Riseman and C. Foster, "The Inhibition of Potential Parallelism by Conditional Jumps," IEEE Trans. on Computer Architectures, vol. C--21, 1972, pp. 1405--1411.
• 15: Tarek M. Taha , D. Scott Wills, An Instruction Throughput Model of Superscalar Processors, Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03), p.156, June 09-11, 2003
• 16: M. D. Hill , A. J. Smith, Evaluating Associativity in CPU Caches, IEEE Transactions on Computers, v.38 n.12, p.1612-1630, December 1989 [doi>10.1109/12.40842]
• 17: Tejas S. Karkhanis , James E. Smith, A First-Order Superscalar Processor Model, Proceedings of the 31st annual international symposium on Computer architecture, p.338, June 19-23, 2004, München, Germany
• 18: "Computer Hardware Understanding Development Tools 2.0 Reference Guide for MacOS X," July 2002.
• 19: J. M. Tendler, et. al., "IBM Power 4: System Microarchitecture," IBM Journal of Research and Development, 2002, pp. 5--26.
• 20: S. Kachigan, Statistical Analysis. New York: Radius Press, 1986.
• 21: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 22: J. M. Mulder and M. Flynn, "An Area Model for On-Chip Memories and its Application," IEEE Journal of Solid-State Circuits, vol. 26, 1991, pp. 98--106.
• 23: Michael J. Flynn, Computer Architecture: Pipelined and Parallel Processor Design, Jones and Bartlett Publishers, Inc., 1995
• 24: Engin Ïpek , Sally A. McKee , Rich Caruana , Bronis R. de Supinski , Martin Schulz, Efficiently exploring architectural design spaces via predictive modeling, Proceedings of the 12th international conference on Architectural support for programming languages and operating systems, October 21-25, 2006, San Jose, California, USA
• 25: S. Eyerman, J. Smith, and L. Eeckhout, "Characterizing the Branch Misprediction Penalty", International Symposium on Performance Analysis of Systems and Software, 2006, pp. 48--58.
• 26: Stijn Eyerman , Lieven Eeckhout , Tejas Karkhanis , James E. Smith, A performance counter architecture for computing accurate CPI components, Proceedings of the 12th international conference on Architectural support for programming languages and operating systems, October 21-25, 2006, San Jose, California, USA

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL

General Terms:
Design, Performance

Keywords:
analytical model, application specific processors, design optimization, energy model, performance model