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Performance pathologies in hardware transactional memory
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ACM SIGARCH Computer Architecture News archive
Volume 35 ,  Issue 2  (May 2007) table of contents
SESSION: Transactions table of contents
Pages: 81 - 91  
Year of Publication: 2007
ISSN:0163-5964
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Authors
Jayaram Bobba  University of Wisconsin, Madison, WI
Kevin E. Moore  University of Wisconsin, Madison, WI
Haris Volos  University of Wisconsin, Madison, WI
Luke Yen  University of Wisconsin, Madison, WI
Mark D. Hill  University of Wisconsin, Madison, WI
Michael M. Swift  University of Wisconsin, Madison, WI
David A. Wood  University of Wisconsin, Madison, WI
Publisher
ACM  New York, NY, USA
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ABSTRACT

Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously proposed HTMs represent three points in this design space: lazy conflict detection, lazy version management, committer wins (LL); eager conflict detection, lazy version management, requester wins (EL); and eager conflict detection, eager version management, and requester stalls with conservative deadlock avoidance (EE). To isolate the effects of these high-level design decisions, we develop a common framework that abstracts away differences in cache write policies, interconnects, and ISA to compare these three design points. Not surprisingly, the relative performance of these systems depends on the workload. Under light transactional loads they perform similarly, but under heavy loads they differ by up to 80%. None of the systems performs best on all of our benchmarks. We identify seven performance pathologies-interactions between workload and system that degrade performance-as the root cause of many performance differences: FriendlyFire, StarvingWriter, SerializedCommit, FutileStall, StarvingElder, RestartConvoy, and DuelingUpgrades. We discuss when and on which systems these pathologies can occur and show that they actually manifest within TM workloads. The insight provided by these pathologies motivated four enhanced systems that often significantly reduce transactional memory overhead. Importantly, by avoiding transaction pathologies, each enhanced system performs well across our suite of benchmarks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, JaeWoong Chung, Lance Hammond, Christos Kozyrakis, and Kunle Olukotun. A Scalable, Non-blocking Approach to Transactional Memory. In Proceedings of the Thirteenth IEEE Symposium on High-Performance Computer Architecture, pages 97--108, February 2007.
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James R. Larus and Ravi Rajwar. Transactional Memory. Morgan & Claypool Publishers, 2006.
 
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Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, and David A. Wood. LogTM: Log-Based Transactional Memory. In Proceedings of the Twelfth IEEE Symposium on High-Performance Computer Architecture, pages 258--269, February 2006.
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Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, and David A. Wood. LogTM-SE: Decoupling Hardware Transactional Memory from Caches. In Proceedings of the Thirteenth IEEE Symposium on High-Performance Computer Architecture, pages 261--272, February 2007.

CITED BY  16

Collaborative Colleagues:
Jayaram Bobba: colleagues
Kevin E. Moore: colleagues
Haris Volos: colleagues
Luke Yen: colleagues
Mark D. Hill: colleagues
Michael M. Swift: colleagues
David A. Wood: colleagues