System level clock tree synthesis for power optimization

ABSTRACT

The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall power dissipations are possible by optimizing the clock tree. Although these savings are already relevant at system-level, only little effort has been made to consider the clock tree at higher levels of abstraction. This paper shows how the clock-tree can be integrated into system-level power estimation and optimization. A clock tree routing algorithm is chosen, adapted to the system-level and then integrated into an algorithmic-level power optimization tool. Experimental results demonstrate the importance of the clock tree for system-level power optimization.

REFERENCES

• 1: ChipVision Design Systems AG. http://www.chipvision.com, 2006. Oldenburg, Germany.
• 2: Rishi Chaturvedi , Jiang Hu, Buffered Clock Tree for High Quality IC Design, Proceedings of the 5th International Symposium on Quality Electronic Design, p.381-386, March 22-24, 2004
• 3: Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , C.-W. Albert Tsao, Bounded-skew clock and Steiner routing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.341-388, July 1998 [doi>10.1145/293625.293628]
• 4: David Duarte , Vijaykrishnan Narayanan , Mary Jane Irwin , Mahmut Kandemir, Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks, Proceedings of the The 14th International Conference on VLSI Design (VLSID '01), p.248, January 03-07, 2001
• 5: Masato Edahiro, An efficient zero-skew routing algorithm, Proceedings of the 31st annual conference on Design automation, p.375-380, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196426]
• 6: K. Kurokawa et al. A high-speed and low-power clock tree synthesis by dynamic clock scheduling. IEICE Transactions on Fundamentals, E85-A(12), December 2002.
• 7: P. E. Gronowski et al. High performance microprocessor design. IEEE Journal on Solid State Circuits, 33, May 1998.
• 8: Tetsuya Yamaday , Masahide Abe , Yusuke Nitta , Kenji Oguray , Manabu Kusaoke , Makoto Ishikawa , Motokazu Ozawa , Kiwamu Tak ada , Fumio Arakawa , Osamu Nishii , T oshihiro Hattori, Low-Power Design of 90-nm SuperH Processor Core, Proceedings of the 2005 International Conference on Computer Design, p.258-266, October 02-05, 2005 [doi>10.1109/ICCD.2005.72]
• 9: E. G. Friedman. Clock distribution networks in synchronous digital integrated circuits. Proceedings of the IEEE, 89(5), May 2001.
• 10: Dennis J. H. Huang , Andrew B. Kahng , Chung-Wen Albert Tsao, On the bounded-skew clock and Steiner routing problems, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.508-513, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217579]
• 11: A. B. Kahng and G. Robbins. On Optimal Interconnections for VLSI. Kluwer, 1994.
• 12: Y. W. Lin, H. Y. Liu, and C. Y. Lee. A 1-gs/s fft/ifft processor for uwb applications. IEEE Journal of Solid State Circuits, 40(8), August 2005.
• 13: Z. Lin and N. K. Jha. Interconnect-aware low power high-level synthesis. IEEE Transactions on CAD of Integrated Circuits and Systems, 24(3), March 2005.
• 14: D Liu and C. Svensson. Power consumption estimation in CMOS VLSI chips. In IEEE Journal of Solid-State Circuits, volume 29, no. 6, pages 663--670, june 1994.
• 15: A. Stammermann , D. Helms , M. Schulte , A. Schulz , W. Nebel, Binding, Allocation and Floorplanning in Low Power High-Level Synthesis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.544, November 09-13, 2003 [doi>10.1109/ICCAD.2003.40]
• 16: Atsushi Takahashi , Kazunori Inoue , Yoji Kajitani, Clock-tree routing realizing a clock-schedule for semi-synchronous circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.260-265, November 09-13, 1997, San Jose, California, United States
• 17: Q. Wu, M. Pedram, and M. X. Wu. Clock-gating and its application to low power design of sequential circuits. IEEE Transactions on Circuits and Systems I, 47(3), March 2000.