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ABSTRACT

Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.

REFERENCES

• 1: Sarvesh Bhardwaj , Sarma B. K. Vrudhula , David Blaauw, "AU: Timing Analysis Under Uncertainty, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.615, November 09-13, 2003 [doi>10.1109/ICCAD.2003.1]
• 2: Stephen Boyd , Lieven Vandenberghe, Convex Optimization, Cambridge University Press, New York, NY, 2004
• 3: Jing-Jia Liou , Kwang-Ting Cheng , Sandip Kundu , Angela Krstic, Fast statistical timing analysis by probabilistic event propagation, Proceedings of the 38th conference on Design automation, p.661-666, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379043]
• 4: Luis Guerra e Silva and Zhenhai Zhu and Joel Phillips and L. Miguel Silveira. Variation-Aware, Library Compatible Delay Modeling Strategy. In Proceedings of the IFIP VLSI-SoC Conference, Nice, France, October 2006.
• 5: Farid N. Najm, On the need for statistical timing analysis, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065781]
• 6: Sari Onaissi , Farid N. Najm, A linear-time approach for static timing analysis covering all process corners, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233545]
• 7: Lou Scheffer, Explicit computation of performance as a function of process variation, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA [doi>10.1145/589411.589413]
• 8: J. Stolfi and L. H. de Figueiredo. Self-Validated Numerical Methods and Applications. In Operations Research, July 1997.
• 9: C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996663]