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HW/SW implementation from abstract architecture models
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Nice, France
TUTORIAL SESSION: Embedded tutorial - EDA - a pivotal theme in the european technology platforms - ARTEMIS and ENIAC table of contents
Pages: 1470 - 1471  
Year of Publication: 2007
ISBN:978-3-9810801-2-4
Author
Ahmed Amine Jerraya  TIMA Laboratory, Grenoble, France
Sponsors
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
: The EDA Consortium
EDAA : European Design and Automation Association
RAS : RAS
: The IEEE Computer Society TTTC
: ECSI
Publisher
EDA Consortium  San Jose, CA, USA
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ABSTRACT

The evolution of technologies is enabling the integration of complex platforms in a single chip; called System-on-Chip, SoC. Modern SoC may include one or several CPU subsystems to execute software and sophisticated interconnect in addition to specific hardware subsystems. This is no more an advanced research topic for academia. 90% of SoCs designed since the start of the 130nm process include at least one CPU. Multimedia platforms (e.g. Nomadik and Nexperia) are already multiprocessor systems-on-chip (MPSoCs) using different kinds of programmable processors (e.g. DSPs and microcontrollers). This trend of building heterogeneous multi-processor SoCs will even accelerate. It is easy to imagine that the design of a SoC with more than a hundred processors will become a current practice in a few years time, e.g. with 45nm technology in 2008. Compared with conventional ASIC design, such a multi-processor SoC is a fundamental change in chip design. These chips will include very sophisticated interconnect such as networks-on-chips (NoC). Moreover, to achieve the required communication performances, each processor may use different local architectures and communication schemes (fast links, non standard memory organization and access).


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
ENIAC Strategic Research Agenda 2005, <http://www.eurosfaire.prd.fr/7pc/doc/1147246667_eniac_strategic_research_agenda_full__2005.pdf>
 
2
ARTEMIS Strategic Research Agenda 2005, <http://www.artemis-office.org/DotNetNuke/Portals/0/Documents/sra.pdf>
 
3
MEDEA+ Design Automation Roadmap 2005, <http://www.medeaplus.org/web/communication/publ_eda.php>
Collaborative Colleagues:
Ahmed Amine Jerraya: colleagues