A low-SER efficient core processor architecture for future technologies

ABSTRACT

Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions have started to be investigated by the community, the full use of future resources in circuits tolerant to SETs, without performance, area or power penalties, is still an open research issue. This paper introduces MemProc, an embedded core processor with extra low SER sensitivity, and with no performance or area penalty when compared to its RISC counterpart. Central to the SER reduction are the use of new magnetic memories (MRAM and FRAM) and the minimization of the combinational logic area in the core. This paper shows the results of fault injection in the MemProc core processor and in a RISC machine, and compares performance and area of both approaches. Experimental results show a 29 times increase in fault tolerance, with up to 3.75 times in performance gains and 14 times less sensible area.

REFERENCES

• 1: Daniele Rossi , Martin Omana , Fabio Toma , Cecilia Metra, Multiple Transient Faults in Logic: An Issue for Next Generation ICs, Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), p.352-360, October 03-05, 2005 [doi>10.1109/DFTVS.2005.47]
• 2: Robert Baumann, Soft Errors in Advanced Computer Systems, IEEE Design & Test, v.22 n.3, p.258-266, May 2005 [doi>10.1109/MDT.2005.69]
• 3: Deepak D. Sherlekar, Design considerations for regular fabrics, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA [doi>10.1145/981066.981087]
• 4: Duncan Elliott , Michael Stumm , W. Martin Snelgrove , Christian Cojocaru , Robert McKenzie, Computational RAM: Implementing Processors in Memory, IEEE Design & Test, v.16 n.1, p.32-41, January 1999 [doi>10.1109/54.748803]
• 5: Semiconductor Industry Association. International Technology Roadmap for Semiconductors - ITRS 2005, last access July, 2006. http://www.itrs.net/Common/2005ITRS/Home2005.htm.
• 6: Eric Rotenberg, AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors, Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, p.84, June 15-18, 1999
• 7: Steven K. Reinhardt , Shubhendu S. Mukherjee, Transient fault detection via simultaneous multithreading, Proceedings of the 27th annual international symposium on Computer architecture, p.25-36, June 2000, Vancouver, British Columbia, Canada
• 8: Alfredo Benso , Silvia Chiusano , Paolo Prinetto, A Self-Repairing Execution Unit for Microprogrammed Processors, IEEE Micro, v.21 n.5, p.16-22, September 2001 [doi>10.1109/40.958696]
• 9: Shlomi Dolev , Yinnon A. Haviv, Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors, IEEE Transactions on Computers, v.55 n.4, p.385-399, April 2006 [doi>10.1109/TC.2006.61]
• 10: Tehrani, S. et al., "Magnetoresistive Random Access Memory using Magnetic Tunnel Junctions", in Proceedings of the IEEE, vol. 91, no. 5, pp 703--714, IEEE Computer Society, London-New York, May 2003. ISSN: 0018--9219.
• 11: Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj, Analytical estimation of transition activity from word-level signal statistics, Proceedings of the 34th annual conference on Design automation, p.582-587, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266289]
• 12: N. Seifert and N. Tam, "Timing Vulnerability Factors of Sequentials," IEEE Trans. Device and Materials Reliability, V4, N3, Sept. 2004, pp. 516--522.
• 13: Shubhendu S. Mukherjee , Joel Emer , Steven K. Reinhardt, The Soft Error Problem: An Architectural Perspective, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.243-247, February 12-16, 2005 [doi>10.1109/HPCA.2005.37]
• 14: Antonio C. S. Beck Filho , Julio C. B. Mattos , Flávio R. Wagner , Luigi Carro, CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator, Proceedings of the 16th symposium on Integrated circuits and systems design, p.349, September 08-11, 2003
• 15: John L. Hennessy , David A. Patterson, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 02
• 16: Subhasish Mitra , Norbert Seifert , Ming Zhang , Quan Shi , Kee Sup Kim, Robust System Design with Built-In Soft-Error Resilience, Computer, v.38 n.2, p.43-52, February 2005 [doi>10.1109/MC.2005.70]
• 17: Last access: July, 2006. http://www.mentor.com/products/fpga_pld/synthesis/leonardo_spectrum/.