Soft error rate analysis for sequential circuits

ABSTRACT

Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensive research has been done so far in modeling and analysis of combinational circuit susceptibility to soft errors, while sequential circuits have received much less attention. In this paper, we present an approach for evaluating the susceptibility of sequential circuits to soft errors. The proposed approach uses symbolic modeling based on BDDs/ADDs and probabilistic sequential circuit analysis. The SER evaluation is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10^-7 FIT) within ten clock cycles after the hit. The results obtained with the proposed symbolic framework are within 4% average error and up to 11000X faster when compared to HSPICE detailed circuit simulation.

REFERENCES

• 1: Subhasish Mitra , Norbert Seifert , Ming Zhang , Quan Shi , Kee Sup Kim, Robust System Design with Built-In Soft-Error Resilience, Computer, v.38 n.2, p.43-52, February 2005 [doi>10.1109/MC.2005.70]
• 2: Robert Baumann, Soft Errors in Advanced Computer Systems, IEEE Design & Test, v.22 n.3, p.258-266, May 2005 [doi>10.1109/MDT.2005.69]
• 3: Premkishore Shivakumar , Michael Kistler , Stephen W. Keckler , Doug Burger , Lorenzo Alvisi, Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic, Proceedings of the 2002 International Conference on Dependable Systems and Networks, p.389-398, June 23-26, 2002
• 4: J. F. Ziegler , H. W. Curtis , H. P. Muhlfeld , C. J. Montrose , B. Chin, IBM experiments in soft fails in computer electronics (1978–1994), IBM Journal of Research and Development, v.40 n.1, p.3-18, Jan. 1996
• 5: Natasa Miskov-Zivanov , Diana Marculescu, MARS-C: modeling and reduction of soft errors in combinational circuits, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1147104]
• 6: Hossein Asadi , Mehdi B. Tahoori, Soft Error Modeling and Protection for Sequential Elements, Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), p.463-474, October 03-05, 2005 [doi>10.1109/DFTVS.2005.61]
• 7: P. Dodd. Basic Mechanisms and Modeling of Single-Event Upset in Digital Microelectronics. In Proc. of the IEEE Transactions on Nuclear Science, Vol. 50, No. 3, pp. 583--602, June 2003.
• 8: D. Marculescu , R. Marculescu , M. Pedram, Trace-driven steady-state probability estimation in FSMs with application to power estimation, Proceedings of the conference on Design, automation and test in Europe, p.774-781, February 23-26, 1998, Le Palais des Congrés de Paris, France
• 9: G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi. Markovian Analysis of Large Finite State Machines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 12, pp. 1479--1493, December 1996.
• 10: Chi-Ying Tsui , José Monteiro , Massoud Pedram , Srinivas Devadas , Alvin M. Despain , Bill Lin, Power estimation methods for sequential logic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.3, p.404-416, Sept. 1995 [doi>10.1109/92.406998]
• 11: Berkeley Predictive Technology Model (BPTM): http://www-device.eecs.berkeley.edu/~ptm.
• 12: Ivan Sutherland , Bob Sproull , David Harris, Logical effort: designing fast CMOS circuits, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1999