Self-heating-aware optimal wire sizing under Elmore delay model

ABSTRACT

Global interconnect temperature keeps rising in the current and future technologies due to self-heating and the adiabatic property of top metal layers. The thermal effects impact adversely both reliability and performance of the interconnect wire, shortening the interconnect lifetime and increasing the interconnect delay. Such effects must be considered during the process of interconnect design. In this paper, one important argument is that the traditional linear dependence between wire resistance and wire width is no longer adequate for high layer interconnects due to the adiabatic property of these wires. By using curve fitting technique, we propose a quadratic model to represent the resistance of interconnect, which is aware of the thermal effects. Based on this model and the Elmore delay model, we derived a linear optimal wire sizing formula in form of f (x) = ax + b. Compared to non-thermal-aware exponential wire sizing formula in form of f (x) = ae^-bx, we observed a 49.7% average delay gain with different choices of physical parameters.

REFERENCES

• 1: Amir H. Ajami , Kaustav Banerjee , Massoud Pedram, Analysis of substrate thermal gradient effects on optimal buffer insertion, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 2: Amir H. Ajami , Kaustav Banerjee , Massoud Pedram , Lukas P. P. P. van Ginneken, Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs, Proceedings of the 38th conference on Design automation, p.567-572, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379025]
• 3: K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu. The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal. In IEDM, 1996.
• 4: K. Banerjee and A. Mehrotra. Global Interconnect Warming. Circuit and Devices, pages 16--32, 2001.
• 5: Kaustav Banerjee , Amit Mehrotra , Alberto Sangiovanni-Vincentelli , Chenming Hu, On thermal effects in deep sub-micron VLSI interconnects, Proceedings of the 36th ACM/IEEE conference on Design automation, p.885-891, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310093]
• 6: A. Bejan. Heat Transfer. John Wiley Sons, Inc, 1993.
• 7: J. R. Black. Electromigration - A brief survey and some recent results. IEEE Transactions on Electron Devices, pages 338--347, 1969.
• 8: M. R. Casu, M. Graziano, G. Piccinini, G. Masera, and M. Zamboni. Effects of Temperature in Deep-Submicron Global Interconnect Optimization. Microelectronic Journal, 2004.
• 9: Chung-Ping Chen , Chris C. N. Chu , D. F. Wong, Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.617-624, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289097]
• 10: Chung-Ping Chen , D. F. Wong, Optimal wire-sizing function with fringing capacitance consideration, Proceedings of the 34th annual conference on Design automation, p.604-607, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266295]
• 11: Chung-Ping Chen , Hai Zhou , D. F. Wong, Optimal non-uniform wire-sizing under the Elmore delay model, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.38-43, November 10-14, 1996, San Jose, California, United States
• 12: D. Chen, E. Li, E. Rosenbaum, and S. Kang. Interconnect Thermal Modeling for Accurate Simulation of Circuit Timing and Reliability. IEEE TCADICAS, 19(2), February 2000.
• 13: Jason Cong , Lei He , Cheng-Kok Koh , Zhigang Pan, Global interconnect sizing and spacing with consideration of coupling capacitance, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.628-633, November 09-13, 1997, San Jose, California, United States
• 14: J. Cong , C. Koh , K. Leung, Simultaneous buffer and wire sizing for performance and power optimization, Proceedings of the 1996 international symposium on Low power electronics and design, p.271-276, August 12-14, 1996, Monterey, California, United States
• 15: Jason Cong , Kwok-Shing Leung, Optimal wiresizing under the distributed Elmore delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.634-639, November 07-11, 1993, Santa Clara, California, United States
• 16: Jason Cong , Kwok-Shing Leung , Dian Zhou, Performance-driven interconnect design based on distributed RC delay model, Proceedings of the 30th international conference on Design automation, p.606-611, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165065]
• 17: W. C. Elmore. The transient response of damped linear networks with particular regard to wide band amplifiers. J. Applied Physics, 1948.
• 18: Youxin Gao , D. F. Wong, Optimal shape function for a bi-directional wire under Elmore delay model, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.622-627, November 09-13, 1997, San Jose, California, United States
• 19: S. Im and K. Banerjee. Full Chip Thermal Analysis of Planar(2-D) and Vertically Integrated(3-D) high-performance ICs. In IEDM, 2000.
• 20: P. Kapur, J. P. McVittie, and K. C. Saraswat. Technology and Reliability Constrained Future Copper Interconnects - Part I: Resistance Modeling. IEEE Transactions on Electron Devices, 49(4), April 2002.
• 21: Noel Menezes , Satyamurthy Pullela , Florentin Dartu , Lawrence T. Pillage, RC interconnect synthesis—a moment fitting approach, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.418-425, November 06-10, 1994, San Jose, California, United States
• 22: Singiresu S. Rao , S. S. Rao, Applied Numerical Methods for Engineers and Scientists, Prentice Hall Professional Technical Reference, 2001
• 23: L. P. P. P. van Ginneken. Buffer placement in distributed RC-tree networks for minimal Elmore delay. In ISCAS, 1990.