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Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Nice, France
SESSION: Compiler techniques for customisable architectures table of contents
Pages: 1337 - 1342  
Year of Publication: 2007
ISBN:978-3-9810801-2-4
Authors
Mehrdad Reshadi  University of California, Irvine, CA
Daniel Gajski  University of California, Irvine, CA
Sponsors
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
: The EDA Consortium
EDAA : European Design and Automation Association
RAS : RAS
: The IEEE Computer Society TTTC
: ECSI
Publisher
EDA Consortium  San Jose, CA, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 27,   Citation Count: 2
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ABSTRACT

The increasing role of software in the embedded systems has made processor an important component in these systems. However, to meet the tight constraints of embedded application, it is often required to customize the processor for the application. Customizing instruction-based processors is difficult and very challenging. Design approaches based on statically-scheduled horizontal-microcoded architectures have been proposed to simplify the architecture customization. In these approaches, first the datapath is specified by the designer, and then the operations of the datapath are extracted automatically. Since the operations are statically scheduled in these architectures (i) low-level programming using assembly is impossible or very tedious; and (ii) execution of programs cannot be interrupted arbitrarily. In this paper, we address the above problems. We show how to efficiently handle interrupts in such architectures and also propose an elegant way of controlling low-level hardware resources in a general way in C language. We also show that after adding interrupt and low-level programming we could use the above architectural style in a multi-core system to implement a complete MP3 decoder that can process 122 frames per second while the standard requirement is 38 frames per seconds.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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B. Gorjiara, M. Reshadi, D. Gajski, "Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs", International Conference on Computer Design (ICCD), October 2006.
 
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MiBench benchmark: http://www.eecs.umich.edu/mibench/
 
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MPEG Audio Decoder: http://www.underbit.com/products/mad/
 
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B. Gorjiara, M. Reshadi, D. Gajski, "NISC Communication-Interfece", Center for Embedded Computer Systems (CECS), TR 05--18, December 2005.
 
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Fraunhofer-Gesellschaft website: ftp://flp.fhg.de/pub/layer3/mp3-bitstreams.tgz
 
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W. Qin and S. Malik, "Architecture Description Languages for Retargetable Compilation", in The Compiler Design Handbook: Optimizations & Machine Code Generation. Y. N. Srikant and Priti Shankar, CRC Press, 2002.
 
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Collaborative Colleagues:
Mehrdad Reshadi: colleagues
Daniel Gajski: colleagues