Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining

ABSTRACT

This paper addresses the problem of interconnect pipelining from both power consumption and bit error rate (BER) point of view and tries to find the optimal solution for a given wire pipelining scheme in nanometer scale very large scale integration technologies. In this paper a detailed analysis for the dependency of power consumption and BER on the number of flip-flops inserted and repeater size is performed. For the best tradeoff between the wire delay, BER and power consumption, a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit. Then this methodology is applied to calculate the optimal solutions for some International Technology Roadmap for Semiconductor technology nodes.

REFERENCES

• 1: Lizheng Zhang , Yuhen Hu , Charlie, Chungping Chen, Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996806]
• 2: R. Lu , G. Zhong , C. Koh , K. Chao, Flip-Flop and Repeater Insertion for Early Interconnect Planning, Proceedings of the conference on Design, automation and test in Europe, p.690, March 04-08, 2002
• 3: Methodologies and Tools for Pipelined On-Chip Interconnect, Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02), p.152, September 16-18, 2002
• 4: V. Nookala, S. S. Sapatnekar, "Designing optimized pipelined global interconnects: Algorithms and methodology impact," IEEE International Symposium on Circuit and systems, Vol.1, pp.608--611, May 2005.
• 5: Jason Cong , Yiping Fan , Zhiru Zhang, Architecture-level synthesis for automatic interconnect pipelining, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996731]
• 6: V. Seth , Min Zhao , Jiang Hu, Exploiting level sensitive latches in wire pipelining, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.283-290, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382587]
• 7: International technology Roadmap for Semiconductors, Semiconductor Research Corporation, 2004
• 8: H. Zhou, C. Lin, "Retiming for Wire Pipelining in System-On-Chip," IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems. Vol.23, Issue 9, pp.1338--1345, September 2004
• 9: Vidyasagar Nookala , Sachin S. Sapatnekar, A method for correcting the functionality of a wire-pipelined circuit, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996724]
• 10: Mario R. Casu , Luca Macchiarulo, A new approach to latency insensitive design, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996725]
• 11: Ashok Jagannathan , Hannah Honghua Yang , Kris Konigsfeld , Dan Milliron , Mosur Mohan , Michail Romesis , Glenn Reinman , Jason Cong, Microarchitecture evaluation with floorplanning and interconnect pipelining, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120879]
• 12: Weiping Liao , Lei He, Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.574, November 09-13, 2003 [doi>10.1109/ICCAD.2003.75]
• 13: Weiping Liao , Lei He, Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.574, November 09-13, 2003 [doi>10.1109/ICCAD.2003.75]
• 14: Antonio G. M. Strollo , Ettore Napoli , Carlo Cimino, Analysis of power dissipation in double edge-triggered flip-flops, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.5, p.624-629, Oct., 2000 [doi>10.1109/92.894168]
• 15: Vladimir Stoanovic and Vojin G. Oklobdzija, "Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems", IEEE Journal of Solid-State Circuits, Vol.34, No.4, Apr. 1999.
• 16: Victor Adler, Eby G. Friedman, "Repeater Design to Reduce Delay and Power in Resistive Interconnect", IEEE Transaction on Circuits and Systems, Vol.45, No.5, May 1998.
• 17: K. Banerjee and A. Mehrotra, "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs", IEEE Transaction on Electron Devices, Vol.49, No.11, Nov. 2002.
• 18: X. Li, J. Mao, H. Huang and Y. Yu, "Global Interconnect Width and Spacing Optimization for Latency, Bandwidth and Power Dissipation", IEEE Transaction on Electron Devices, Vol.52, No. 10, Oct.2005
• 19: M. L. Mui, K. Banerjee, A. Mehrotra, "A Global Inerconnect Optimization Scheme for Nanometer Scale VLSI Width Implications for Latency, Bandwidth and Power "Dissipatoin", IEEE Transaction on Electron Devices, Vol.51, No.2, Feb. 2004
• 20: H. B. Bakoglu, "Circuits, Interconnections and Packaging for VLST", Reading, MA: Addision-Wesley, 1990.