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Test quality analysis and improvement for an embedded asynchronous FIFO
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Nice, France
SESSION: Nano and FIFO table of contents
Pages: 859 - 864  
Year of Publication: 2007
ISBN:978-3-9810801-2-4
Authors
Tobias Dubois  Linköpings Universitet, Embedded Systems Laboratory, Sweden
Erik Jan Marinissen  NXP Semiconductors Research, The Netherlands
Mohamed Azimane  NXP Semiconductors Research, The Netherlands
Paul Wielage  NXP Semiconductors Research, The Netherlands and currently with NXP Semiconductors' IC Laboratory in Eindhoven, The Netherlands
Erik Larsson  Linköpings Universitet, Embedded Systems Laboratory, Sweden
Clemens Wouters  NXP Semiconductors, Digital Library Technology, The Netherlands
Sponsors
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
: The EDA Consortium
EDAA : European Design and Automation Association
RAS : RAS
: The IEEE Computer Society TTTC
: ECSI
Publisher
EDA Consortium  San Jose, CA, USA
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ABSTRACT

Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clocks, which is at least a factor two smaller and also faster than SRAM-based and standard-cell-based counterparts. The detection qualities of the FIFO test for both hard and weak resistive shorts and opens have been analyzed by an IFA-like method based on analog simulation. The defect coverage of the initial FIFO test for shorts in the bit-cell matrix has been improved by inclusion of an additional data background and low-voltage testing; for low-resistant shorts, 100% defect coverage is obtained. The defect coverage for opens has been improved by a new test procedure which includes waiting periods.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J. P. Shen, W. Maly, and F. J. Ferguson. Inductive Fault Analysis of MOS Integrated Circuits. IEEE Design & Test of Computers, 2(6):13--26, December 1985.
 
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Jose Pineda de Gyvez. IC Defect Sensitivity for Footprint-Type Spot Defects. IEEE Transactions on Computer-Aided Design, 11(5):638--658, May 1992.
 
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Collaborative Colleagues:
Tobias Dubois: colleagues
Erik Jan Marinissen: colleagues
Mohamed Azimane: colleagues
Paul Wielage: colleagues
Erik Larsson: colleagues
Clemens Wouters: colleagues