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Interactive presentation: Soft-core processor customization using the design of experiments paradigm
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Nice, France
SESSION: Advanced techniques for embedded processors design table of contents
Pages: 821 - 826  
Year of Publication: 2007
ISBN:978-3-9810801-2-4
Authors
David Sheldon  University of California, Riverside
Frank Vahid  UC Irvine
Stefano Lonardi  University of California, Riverside
Sponsors
: IEEE Council on Electronic Design Automation (CEDA)
SIGDA: ACM Special Interest Group on Design Automation
: The EDA Consortium
EDAA : European Design and Automation Association
RAS : RAS
: The IEEE Computer Society TTTC
: ECSI
Publisher
EDA Consortium  San Jose, CA, USA
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ABSTRACT

Parameterized components are becoming more commonplace in system design. The process of customizing parameter values for a particular application, called tuning, can be a challenging task for a designer. Here we focus on the problem of tuning a parameterized soft-core microprocessor to achieve the best performance on a particular application, subject to size constraints. We map the tuning problem to a well-established statistical paradigm called Design of Experiments (DoE), which involves the design of a carefully selected set of experiments and a sophisticated analysis that has the objective to extract the maximum amount of information about the effects of the input parameters on the experiment. We apply the DoE method to analyze the relation between input parameters and the performance of a soft-core microprocessor for a particular application, using only a small number of synthesis/execution runs. The information gained by the analysis in turn drives a soft-core tuning heuristic. We show that using DoE to sort the parameters in order of impact results in application speedups of 6x-17x versus an un-tuned base soft-core. When compared to a previous single-factor tuning method, the DoE-based method achieves 3x-6x application speedups, while requiring about the same tuning runtime. We also show that tuning runtime can be reduced by 40--45% by using predictive tuning methods already built into a DoE tool.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
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Altera Corp. Nios II Processors, http://www.altera.com/products/ip/processors/nios2/ni2-index.html, 2005.
 
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Givargis, T., F. Vahid. Platune: A Tuning Framework for System-on-a-Chip Platforms. IEEE Transactions on Computer Aided Design, Vol. 21, No. 11, Nov. 2002, pp. 1317--1327.
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Petersen, R., Design and Analysis of Experiments. Mercel Dekker Inc. New York, New York, 1985.
 
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Xilinx, Inc. MicroBlaze Soft Processor Core. http://www.xilinx.com/, 2005.
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Collaborative Colleagues:
David Sheldon: colleagues
Frank Vahid: colleagues
Stefano Lonardi: colleagues