| Interactive presentation: Soft-core processor customization using the design of experiments paradigm |
| Full text |
Pdf
(100 KB)
|
| Source
|
Design, Automation, and Test in Europe
archive
Proceedings of the conference on Design, automation and test in Europe
table of contents
Nice, France
SESSION: Advanced techniques for embedded processors design
table of contents
Pages: 821 - 826
Year of Publication: 2007
ISBN:978-3-9810801-2-4
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
EDA Consortium
San Jose, CA, USA
|
| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 27, Citation Count: 0
|
|
|
ABSTRACT
Parameterized components are becoming more commonplace in system design. The process of customizing parameter values for a particular application, called tuning, can be a challenging task for a designer. Here we focus on the problem of tuning a parameterized soft-core microprocessor to achieve the best performance on a particular application, subject to size constraints. We map the tuning problem to a well-established statistical paradigm called Design of Experiments (DoE), which involves the design of a carefully selected set of experiments and a sophisticated analysis that has the objective to extract the maximum amount of information about the effects of the input parameters on the experiment. We apply the DoE method to analyze the relation between input parameters and the performance of a soft-core microprocessor for a particular application, using only a small number of synthesis/execution runs. The information gained by the analysis in turn drives a soft-core tuning heuristic. We show that using DoE to sort the parameters in order of impact results in application speedups of 6x-17x versus an un-tuned base soft-core. When compared to a previous single-factor tuning method, the DoE-based method achieves 3x-6x application speedups, while requiring about the same tuning runtime. We also show that tuning runtime can be reduced by 40--45% by using predictive tuning methods already built into a DoE tool.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Arm http://www.arm.com.
|
| |
2
|
Altera Corp. Nios II Processors, http://www.altera.com/products/ip/processors/nios2/ni2-index.html, 2005.
|
| |
3
|
DOE Pro XL http://sigmazone.com/doepro_faqs.htm.
|
| |
4
|
EEMBC. http://www.eembc.org/, 2005.
|
| |
5
|
Givargis, T., F. Vahid. Platune: A Tuning Framework for System-on-a-Chip Platforms. IEEE Transactions on Computer Aided Design, Vol. 21, No. 11, Nov. 2002, pp. 1317--1327.
|
 |
6
|
|
 |
7
|
Rakesh Kumar , Dean M. Tullsen , Parthasarathy Ranganathan , Norman P. Jouppi , Keith I. Farkas, Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance, Proceedings of the 31st annual international symposium on Computer architecture, p.64, June 19-23, 2004, München, Germany
|
| |
8
|
McLean, R., V. Anderson, Applied Factorial and Fractional Designs. Marcel Dekker, Inc. New York, New York, 1984.
|
| |
9
|
Moyer, B., Tune Multicore Hardware for Software. Xcell Journal, Issue 58, 2006, pp 55--57.
|
| |
10
|
Petersen, R., Design and Analysis of Experiments. Mercel Dekker Inc. New York, New York, 1985.
|
| |
11
|
|
 |
12
|
David Sheldon , Rakesh Kumar , Roman Lysecky , Frank Vahid , Dean Tullsen, Application-specific customization of parameterized FPGA soft-core processors, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
[doi> 10.1145/1233501.1233553]
|
| |
13
|
Tensilica, Inc. The XPRES Compiler: Triple-Threat Solution to Code Performance Challenges. http://www.tensilica.com/pdf/XPRES-Triple-Threat_Solution.pdf, 2005.
|
| |
14
|
Xilinx, Inc. MicroBlaze Soft Processor Core. http://www.xilinx.com/, 2005.
|
 |
15
|
|
 |
16
|
Peter Yiannacouras , Jonathan Rose , J. Gregory Steffan, The microarchitecture of FPGA-based soft processors, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
[doi> 10.1145/1086297.1086325]
|
|