| CATS: cycle accurate transaction-driven simulation with multiple processor simulators |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe
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Nice, France
SESSION: Novel directions in architectural simulation and validation
table of contents
Pages: 749 - 754
Year of Publication: 2007
ISBN:978-3-9810801-2-4
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EDA Consortium
San Jose, CA, USA
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Downloads (6 Weeks): 1, Downloads (12 Months): 43, Citation Count: 3
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ABSTRACT
This paper focuses on enhancing performance of cycle accurate simulation with multiple processor simulators. Simulation performance is determined by how often simulators exchange events with one another and how accurately simulators model their behavior. Previous techniques have limited their applicability or sacrificed accuracy for performance. In this paper, we notice that inaccuracy comes from events which arrive between event exchange boundaries. To solve the problem, we propose cycle accurate transaction-driven simulation which maintains event exchange boundaries at bus transactions but compensates for accuracy. The proposed technique is implemented in a publicly available CATS framework and our experiment with 64 processors achieves 1.2M processor cycles/s (200K instructions/s) which is faster than other cycle accurate frameworks by an order of magnitude.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CATS Framework, http://mesl.ucsd.edu/dhkim/CATS
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Doug Burger and Todd M. Austin, "The SimpleScalar Toolset, Version 2.0," University of Wisconsin-Madison Computer Sciences Department Technical Report #1342, June 1997.
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Steven Cameron Woo , Moriyoshi Ohara , Evan Torrie , Jaswinder Pal Singh , Anoop Gupta, The SPLASH-2 programs: characterization and methodological considerations, Proceedings of the 22nd annual international symposium on Computer architecture, p.24-36, June 22-24, 1995, S. Margherita Ligure, Italy
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Nathan L. Binkert, Erik G. Hallnor, and Steven K. Reinhardt, "Network-Oriented Full-System Simulation using M5", Proceedings of the Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads, Feb 2003.
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Chris Lennard, Davorin Mista, "Taking Design to the System Level", the white paper for SoC Designer, a ARM Inc.
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"AMBA Specification Rev 2.0", ARM Inc.
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CITED BY 3
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Hyunhee Kim , Sungjun Youn , Jihong Kim, A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches, Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, p.30-37, October 26-26, 2008, Toronto, Canada
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